A single-chip microcomputer connectable to an external memory for expanding the address space, and having a first mode of operation in which the available memory region is both the region of an internal ROM and the external memory, and having a second mode of operation in which the available memory region is the region of the external memory only. An inhibiting device is provided for inhibiting the switching from the second mode to the first mode, thereby ensuring that the contents of the internal ROM cannot be read-out.

Single chip microcomputer having unauthorized memory space access protection

To increase the versatility of a central processing unit (30) controlling an operating apparatus, such as apparatus including an engine, installed in an automotive vehicle, a main read-only memory (ROM, 40) stores not only operating data of the vehicle and/or the engine, but additionally, the organization program of the central processing unit (CPU, 30) in modular, or block form in the ROM (40). An auxiliary ROM (41) preferably an electronically erasable ROM is connectable, via an interconnection bus (80) to the CPU (30) and an initial program stored in the main ROM (40) provides a determination or recognition step to be carried out by the CPU (30) first, to determine if the auxiliary EPROM (41) is present; and, if so, to then address the auxiliary EPROM (41) for control of the program run of the CPU; if not, to take programming operating data directly from the ROM (40). The programming stored in the auxiliary EPROM (41) may direct the CPU (30) to carry out programming steps stored in the main ROM (40) in the stored sequence, or in changed sequences, as well as to take operating steps directly from the auxiliary EPROM (41). All programming data are stored in the auxiliary EPROM (41) also in modular or block form, and preferably include diagnostic programs relating to monitoring a function of the vehicle or of the engine, under control of data computed by the CPU (30).

Control system to control operation of an apparatus, more particularly operation of an automotive vehicle

A single-chip microcomputer is disclosed, which comprises a central processing unit including a programmable counter for storing address data for accessing a first memory and performing operations and control, a register for setting address data of a second memory and a coincidence circuit When the contents of the register and programmable counter coincide, the coincidence circuit provides an instruction to the central processing unit Thus, the central processing unit accesses an address of the second memory in lieu of an address of the first memory, in which an undesired instruction in stored, according to data in the first memory Subsequently, the second memory address is accessed in lieu of the first memory address with the undesired instruction therein

Single-chip microcomputer with memory patching capability

A one-chip microcomputer system includes a one-chip microcomputer, a nonvolatile memory which can electrically rewritably store changing data of a program stored in a mask ROM of the one-chip microcomputer, an input unit (connection unit) for receiving data to be written in the nonvolatile memory from an external device, and an object to be controlled by the one-chip microcomputer. In one aspect, the nonvolatile memory has first and second correction data areas, and first and second memories for respectively designating these areas. Upon reception of an initialization signal from the external device connected to the input unit, only the second memory for designating the second correction data area is initialized. In another aspect, the mask ROM stores ROM version data, and the nonvolatile memory stores board version data. Upon writing of the data via the input unit, bug correction data is selected based on the ROM version data and the board version data, and the selected data is written in the nonvolatile memory. In still another aspect, the nonvolatile memory has a first area for storing data for correcting a bug in the program, a second area for storing data for changing a specification of the object to be controlled, and a third area for determining whether or not data are stored in the first and second areas.

One-chip microcomputer system having function for substantially correcting contents of program

A single-chip microcomputer includes therein an electrically programmable read-only memory (EPROM) including a specific cell of the EPROM storing an item of information for discrimination of memory space. When a reset signal is applied for initializing the single-chip microcomputer, the specific cell of the EPROM is selected and read out, and further latched in a latch circuit. On the basis of the content of the latch circuit, the single-chip microcomputer discriminates and sets a boundary between an internal memory and an external memory during programmed operation.

Single-chip microcomputer including an eprom capable of accommodating different memory capacities by address boundary discrimination

A computer having a main read only memory is so arranged that a portion of the information stored in the main read only memory can be changed, if desired, without changing the entire main memory. Information to be substituted for a portion of the main information contained in the main memory is stored in a correction memory, which is incorporated in the computer when required. The CPU is arranged to fetch and use instructions or data alternatively from the main memory or the correction memory in such a manner that a predetermined portion of the main information is replaced by the substitute information. In one embodiment, data is stored in the correction memory for designating which portion is to be replaced and the CPU selects either memory depending upon this data. In another embodiment, one or more comparators are used for comparing the value on an address bus with addresses for designating the start and the end of the portion to be replaced.

Computer having correctable read only memory

PURPOSE:To realize a correction at any part of the storage contents of a main ROM, by discriminating whether a correcting ROM is packaged and then using the program of the correcting ROM only when the said ROM is packaged. CONSTITUTION:For a controller of an internal combustion engine, etc. using a microcomputer, a CPU30 works based on the program stored in a main ROM41 to give an arithmetic process to various types of input signals 10 based on the data converted into the digital signal or the data of the ROM41. The intermediate data is temporarily stored in an RAM50 to be processed, and the result of this process is converted into an output signal 70 via an output circuit 60 to be dilivered. In this case, a discrimination signal 11 is read into each block of the program of the ROM41. And the jumping is given to the program of a correcting ROM42 when the logic 1 is detected. Then an arithmetic process is carried out based on the program or data stored in the ROM42.

Akio Hosaka

Papers

Computer having correctable read only memory

Computer capable of using correcting memory