From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

The concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples. >

A yield improvement technique for IC layout using local design rules

With the shrinking of feature size on silicon, the coupled capacitance between adjacent wires is contributing a significant factor to the interconnect delay, which already dominates the circuit performance. In the near future coupled capacitance could contribute as much as 50-75% to the interconnect delay which has been largely ignored by performance-oriented layout tools. Given a routed design, this work minimizes the delay and the peak cross-talk by re-adjusting the space between interconnects. It can reduce the circuit delay significantly and, in addition, reduce the peak cross-talk problem. An efficient technique based on the network simplex algorithm is used to solve the problem in the paradigm of compaction.

A spacing algorithm for performance enhancement and cross-talk reduction

This paper proposes one-dimensional spacing algorithms that minimize [maximize] the degree of separation [proximity] among the specified elements of a given integrated circuit layout. Number of problems on chip and MCM systems such as poor performance, higher crosstalk, lower yield etc. are related to the degree of separation [proximity]. The proposed algorithms utilize the attractive [repulsive] constraints to shrink [expand] the distances among the specified elements while keeping the layout free of any design rule errors. The spacing problem is reduced to a parametric linear programming problem and a network simplex algorithm is proposed for solving it. The proposed algorithms are implemented into a system called PERFECT for performance enhancement and crosstalk reduction. Given a routed design, PERFECT minimizes delay due to the coupled capacitance, which could contribute as much as 50-75% to the interconnect delay in near future. PERFECT utilizes the repulsive constraints between interconnect segments for the purpose. The experimental results show a significant delay improvement and the crosstalk reduction for submicron technologies. >

Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's

The interwire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called crosstalk constraints, are usually given in the design specification. This paper proposes a crosstalk minimization technique based on segment rearrangement for gridded channel routing. The technique repeatedly rearranges horizontal wire segments and/or increase the number of tracks to satisfy the crosstalk constraints. With experiments, we observed that the presented technique is more effective than the track permutation technique.

COP: a Crosstalk OPtimizer for gridded channel routing

A one-dimensional compaction algorithm with attractive and repulsive constraints is proposed. Depending on these constraints, the proposed algorithm shrinks[expands] the spaces among the specified layout elements without causing any design rule violations, as if some force were affecting them. It implies that the resultant layout has less cross talk and delay. The proposed network simplex algorithm experimentally proves to be efficient in both time and space.

Akira Onozawa

Papers

Layout compaction with attractive and repulsive constraints