The paper consists of three parts. In the first part we review the basic experimental and theoretical results which shaped our present knowledge on point defects and diffusion processes in silicon. These results concern on one side oxidation effects which established that silicon self-interstitials and vacancies coexist in silicon and on the other side diffusion of gold into dislocation-free silicon which allowed to determine the self-interstitial contribution to silicon self-diffusion and to estimate the corresponding vacancy contribution. In the second part we discuss topics for which an understanding is just emerging within the framework of coexisting self-interstitials and vacancies: reaching of local dynamical equilibrium between self-interstitials and vacancies; rough estimates of the thermal equilibrium concentrations of self-interstitials and vacancies and their respective diffusivities, and finally, various possibilities to generate an undersaturation of self-interstitials. In the third part we examine swirl defect formation in silicon in terms of vacancies and self-interstitials.

Point defects, diffusion processes, and swirl defect formation in silicon

Glass substrates suitable for thin film processing can be batch heated to processing temperatures and batch cooled after processing by radiant heating and cooling in a vacuum chamber. The heating and/or cooling chamber is fitted with a cassette including heat conductive shelves that can be heated or cooled, interleaved by the glass substrates mounted on supports so that a gap exists between the shelves and the substrates. As the shelves provide heating or cooling, the glass substrates are radiantly heated or cooled by the shelves, thereby providing uniform heating or cooling of the glass substrates so as to avoid damage or warpage of the substrates. A vacuum system for processing the substrates includes batch-type heating and cooling of the substrates using the chambers of the invention in combination with one-at-a-time film processing chambers that can deposit one or more thin films on the substrates.

Method of heating and cooling large area glass substrates

2 – Diffusion in Silicon and Germanium

A silicon single crystal wafer is subjected to two-stage heat treatment. In the first-stage it is heated at a temperature within the range of between 500° C. and 1,000° C. Subsequently the thus heated wafer is heated at a temperature higher than that at the first stage. Thus, a nondefective zone is formed in the surface region of the wafer, and the interior zone of the wafer becomes rich in micro defects capable of gettering impurities such as heavy metals.

Method of forming nondefective zone in silicon single crystal wafer by two stage-heat treatment

The kinetics of self‐interstitials in silicon were investigated by monitoring oxidation stacking faults on backside oxidized silicon wafers in the temperature range 1100–1200 °C in a wet O2 ambient. The diffusion coefficient and thermal equilibrium concentration of self‐interstitials were obtained by optimizing model parameters to match calculated and experimental observations of growth of oxidation stacking faults at the front surface of silicon wafers protected from oxidation by a composite SiO2/poly Si/Si3N4 film.

Kinetics of self‐interstitials generated at the Si/SiO2 interface

In a method of making a semiconductor device, a semiconductor wafer having a stacking fault originally contained in the wafer or produced in the wafer through the thermal oxidation of the wafer surface is subjected to an annealing treatment in a non-oxidative atmosphere to eliminate the stacking fault. A PN junction is thereafter formed in an area of the wafer from which the stacking fault is eliminated.

Method of making semiconductor device with PN junction in stacking-fault free zone

Shrinkage and annihilation of oxidation‐induced stacking faults in silicon have been investigated by means of combined methods of successive annealing in nitrogen atmosphere and etching technique. The shrinkage rates were measured and the activation energies for shrinkage were determined to be 4.1 and 4.9 eV for (111) and (100) surfaces, respectively. Experimental results are interpreted in terms of climbing of a Frank loop, indicating that the shrinkage process is governed by a mechanism in connection with the self‐diffusion of silicon. A novel gettering technique is proposed.

Shrinkage and annihilation of stacking faults in silicon

In a method of heat-treating a number of wafers each of which consists of a substance of poor heat conduction and a semiconductor layer formed on one surface of the substance, a method of heat treatment of wafers characterized in that the heat treatment is carried out under the state under which an auxiliary wafer made of a substance of good heat conduction is held in proximity to the other surface of the substance of poor heat conduction, whereby the wafers for the heat treatment are prevented from being cracked and have the characteristics made uniform.

Method of heat treatment of wafers

The nonuniform temperatures that develop over silicon wafers on insertion and removal from the furnaces used in the oxidation and diffusion processes of semiconductor fabrication are one factor in reduced yields. For example, because of temperature differences in the oxidation process there are thermal stresses and differing thermal hystereses over the wafer surface which degrade the uniformity of the oxide layer formed. The most pronounced temperature differences, occurring when the wafers are inserted into the furnace, develop mainly because of the effect of the boat jig which supports the wafers. Since the heat capacity of the boat is much greater than that of the wafers, during the slower rise in the boat temperature radiant heat exchange with the wafer bottoms keeps the temperature of the bottoms lower than the temperature of the wafer tops, which are almost unaffected by the boat. This transient in the wafer temperature depends on such process parameters as the boat insertion speed, the ratio between the wafer and furnace reactor tube diameters, and the wafer spacing. In order to analyze this temperature characteristic the process is modelled and the results of numerical simulation are compared with experiment. The model for the wafer temperatures inside the furnace is a system of coupled partial differential equations for the mostly radiant heat fluxes of the boat and wafers. With an insertion speed of 2 m/sec, both the experimental data and the model give a maximum temperature difference over the wafer surface of 230°C near the end of insertion, thus confirming the model.

Akira Yoshinaka

Papers

Method of making semiconductor device with PN junction in stacking-fault free zone

Shrinkage and annihilation of stacking faults in silicon

Method of heat treatment of wafers

Transient model of wafer temperature in a furnace for semiconductor fabrication process

Relaxation process of interfacial misfit between homoepitaxial silicon crystals