A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

High power MOSFET with low on-resistance and high breakdown voltage

An N-channel MOSFET is fabricated with its source, body and gate connected together and biased at a positive voltage with respect to its drain. The resulting two-terminal device functions generally in the manner of a diode but has a significantly lower turn-on voltage than a conventional PN diode. The device is therefore referred to as a "pseudo-Schottky diode". Pseudo-Schottky diodes have numerous uses, but they are particularly useful when connected to shunt current from a conventional PN diode or MOSFET and thereby prevent such conditions as snapback and latchup which can result from the storage of minority carriers in a forward-biased PN junction. Also, because the pseudo-Schottky diode is a majority carrier device, the diode recovery time, amount of stored charge, and peak reverse current are much lower than in a conventional PN diode.

Pseudo-Schottky diode

A high power MOSFET is disclosed in which a plurality of hexagonal base regions formed in the surface of a chip receive respective hexagonal annular source regions. The base regions are relatively shallow and of relatively low conductivity material. A central portion of each of the base regions reaches the upper surface of the wafer and contacts a sheet source electrode which also contacts the source regions. The central regions of the base elements which contact the source electrode are of higher conductivity than the main base portion for a distance extending just below the depth of the source regions. The base regions are formed by ion implantation through a gate oxide which is exposed by a window in an overlying polysilicon layer. After ion implantation and driving of the base regions, an annular source region is diffused into each base, employing the same polysilicon window as an outer mask. A central oxide dot may be left in the center of each of the open windows so that the oxide is thicker at the central regions and remains in place during the diffusion of the source regions.

Semiconductor high-power mosfet device

A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.

Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide

An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.

Monolithic semiconductor switching device

An insulated gate field effect transistor is formed of a drain region of a first conductivity type which faces both of the major surfaces of a semiconductor substrate, a frame region of a second conductivity type which faces the one major surface of the semiconductor substrate, a base region of the second conductivity type which faces the one major surface and is connected to the frame region, a PN junction being formed between the base region and the drain region, and a source region of the first conductivity type which faces the one major surface and is formed in the base region as if being surrounded thereby. The insulated gate field effect transistor is also provided with a source electrode which short-circuits the frame region and the source region, a drain electrode which is provided on the drain region facing the other major surface of the substrate, and a gate electrode which is provided on the base region facing the one major surface through a gate insulating layer.

Insulated gate field effect transistor

A junction gated field effect transistor having a substrate providing a drain region of low impurity concentration, a mosaic shaped gate region of high impurity concentration formed on the drain region, a corresponding mosaic shaped insulating layer overlying said mosaic shaped gate region but having windows therein smaller than the windows of the gate region, the windows of the insulating layer being aligned with the windows of the gate region, a gate electrode connected to said mosaic shaped gate region, a plurality of source regions of high impurity concentration formed on the substrate in the openings of the mesh forming the insulating layer, and a conductive plate source electrode overlying said insulating layer and in contact with said source regions.

Junction gated field effect transistor

A multi-channel junction gated field effect transistor which gives good triode characteristics is formed on a substrate of semiconductor material of relatively low impurity concentration of a first conductivity type. A mosaic shape semiconductor gate region of the opposite conductivity type is formed in the substrate below one major surface thereof, the mosaic shape of the gate region forming a plurality of windows filled with portions of the substrate which thus provide channels leading to the main body of the substrate, the main body of the substrate providing the drain region for the transistor. A corresponding relatively thick mosaic shape insulating layer overlies the mosaic shape gate region has a plurality of windows, which windows are smaller than the windows of the gate region and of the same configuration, the windows of the insulating layer being aligned with the windows of the gate region. The source consists of two regions, one which is heavily doped with impurity of the first conductivity type and the second which has less doping than that of the first source region but of greater doping than the drain region and the channel regions. The first source region is completely within the windows of the insulating layer, while the second source region is partially within such windows and extends down as a tongue partially into the channel. Electrodes are provided for the source, gate and drain regions. The substrate is preferably N-type silicon having a doping level of 1014 to 1015 atoms/cm3. The first source region preferably has a doping higher than 5 × 1019, while the second source region with its tongues has a doping level between 1016 and 1018 atoms/cm3. If the doping level of the second source region is 1018 atoms/cm3, it is possible to have the substrate doped to 1016 atoms/cm3.

Multi-channel junction gated field effect transistor and method of making same

not available for EP0166112Abstract of corresponding document: US4982247A semiconductor device, such as a GaAs FET, has low-noise, ultra-high frequency operation. The semiconductor device has at least one bonding pad for applying potential to the gate electrode lying outside of the source region. In practice, one or more bonding pads are deposited in the general vicinity of the gate electrode and outside of the source region. This allows the number of supply points P to be increased without lengthening the source region and thus expanding the chip. With regard to the drain-gate capacitance, the bonding pad or pads can be surrounded by an electrode other than the drain region electrode or the gate electrode to ensure that the drain-gate capacitance is not increased.

Semiconductor device with bonding pads surrounded by source and/or drain regions

A semiconductor device, such as a GaAs FET, has low-noise, ultra-high frequency operation. The semiconductor device has at least one bonding pad for applying potential to the gate electrode lying outside of the source region. In practice, one or more bonding pads are deposited in the general vicinity of the gate electrode and outside of the source region. This allows the number of supply points P to be increased without lengthening the source region and thus expanding the chip. With regard to the drain-gate capacitance, the bonding pad or pads can be surrounded by an electrode other than the drain region electrode or the gate electrode to ensure that the drain-gate capacitance is not increased.

Akiyasu Ishitani

Papers

Insulated gate field effect transistor

Junction gated field effect transistor

Multi-channel junction gated field effect transistor and method of making same

Semiconductor device with bonding pads surrounded by source and/or drain regions

Semi-conductor device