An architectural co-synthesis algorithm for energy-aware Network-on-Chip design

Due to technology scaling, it is expected that future chips would integrate tens to hundreds of functional units. The growing power and design costs limit the benefit of continuously increasing the universality and complexity of these units and motivate the usage of specialized hardware modules. These modules are likely to be replicated in order to exploit the inherent parallelism of many tasks. This trend already exists in CMPs (moving from multi-core to many-cores), ASSPs and FPGAs. In this paper, we revisit the network on-chip (NoC) mapping problem in light of this expected trend. Specifically, we leverage the use of on-chip replicated specialized modules to minimize traffic and hence to reduce the power consumed by the NoC. We further improve the interconnect efficiency by making the mapping algorithm aware of the set of modules traversed by application data. To this end, we present an enhanced modeling of the resources and timing requirements within a system on-chip (SoC). We evaluate the benefit of the proposed approach and show a significant reduction in the cost of communication.

/pdf/the-era-of-many-modules-soc-revisiting-the-noc-mapping-3xtpxwampa.pdf

The era of many-modules SoC: revisiting the NoC mapping problem

Most streaming applications, such as multimedia and digital signal processing (DSP) application, are iterative in nature, so pipelined implementation can be introduced into streaming application for high throughput. In this case, as a communication-centric design approach, NoC is capable of solv- ing communication bottleneck incurred by throughput increment. In this paper streaming application with pipelined implementa- tion was mapped onto the NoC architecture by an energy-aware mapping algorithm proposed focusing on the pipelining mecha- nism. This algorithm performs the task allocation, scheduling and communication scheduling simultaneously and minimizes the energy consumption. The result generated by this algorithm was verified by a cycle-accurate simulator written in SystemC. Ex- perimental results show that 7 times throughput increments can be achieved and energy consumption is also reduced by 12%, compared with one that doesn't involve pipelined implementation.

Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip

The number of applications executing on multimedia systems is increasing every year. These applications execute in different combinations, known as use-cases. Each application may require guarantees on its performance. Ensuring that all applications meet their throughput requirements in all use-cases with minimum silicon area is a design challenge. In this paper, we present a novel heuristic algorithm that can design MPSoC platforms and map tasks of multiple applications onto this platform while satisfying the throughput constraints of these applications. Our algorithm tries to achieve this goal with minimum hardware area. It exploits the mutual exclusion conditions for concurrent execution of applications, as specified with the use-cases, and allows sharing of resources between multiple applications. There are a number of other techniques (load balancing etc.) that also save resources by sharing them but the feature that distinguishes our work from other related techniques is the fact that in minimization of hardware resources, we not only optimize the computation resources but also optimize the memory and buffer requirements in the interconnect.

http://ieeexplore.ieee.org/iel7/6766338/6778084/06778132.pdf

Designing MPSoC platforms for throughput constrained applications with multiple use-cases

Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of SoC (System-on-Chip) design in deep submicron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of PEs (Processing Elements) with multiple types and their topology. The software architecture contains the allocation of tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. Previous works on NoC design have concentrated on solving for only one or two design parameters at a time. In this paper, we propose a hardware-software co-synthesis algorithm for a heterogeneous NoC architecture. The design goal is to minimize energy consumption while meeting the real-time requirements commonly seen in the embedded applications.

Alan P. Su

Papers

An architectural co-synthesis algorithm for energy-aware network-on-chip design