A method of decoding a video signal is disclosed. The present invention includes obtaining identification information indicating whether a coded picture of a current NAL unit is an inter-view picture group, obtaining interview reference information of the inter-view picture group, and constructing a reference picture list for inter-view prediction using the inter-view reference information according to the identification information, wherein the inter-view reference information includes view identification information of an inter-view reference picture.

Method and apparatus for decoding/encoding a video signal

First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

Methods for defining contact grid in dynamic array architecture

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of V dd , multiple voltage thresholding V t , signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi V dd FPGA.

Low-power FPGA circuits and methods

A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Methods for multi-wire routing and apparatus implementing same

A method of selecting device (14-16, 18-24, 28-30) threshold voltages for high speed and low overall power involves identifying (42) the critical paths by predetermined timing criteria. All transistors have an initial, typically high, threshold voltage (40). Transistors outside the critical paths keep the initial high threshold voltages to minimize static power drain. The transistors in the critical path are selected (43) according to a predetermined sorting function to have a low threshold voltage and thereby switch faster. Although the lower threshold voltage devices consume more static power in standby mode, the power drain is accepted as a trade-off in favor of increased speed through the critical path. The supply voltage is reduced to minimize dynamic power. The integrated circuit is thus optimized to run at a higher frequency with lower overall power consumption.

Method of selecting device threshold voltages for high speed and low power

A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the data input is not changing consumes power without providing a useful function. The switching circuit passes clock pulses to a clock input of the flip-flop only when new data is present to be latched into the flip-flop, i.e. data input state and data output state disagree. The switching circuit blocks clock pulses to the flip-flop when the data to the flip-flop is not changing and thereby saves power consumption.

Low power flip-flop circuit and method thereof

A method of generating power vectors to calculate power dissipation for a circuit cell is provided. The method involves formulating the Boolean equations (30) that describe the logical operation for a circuit cell (10). Primitive power vectors that cause an output to transition are generated (32) using Boolean difference functions. Internal power vectors that cause an internal node to transition without transitioning the output are generated (34) using Boolean difference functions. Static power vectors with all possible steady state inputs are also generated (36). The power vectors are minimized (38) to eliminate redundant vectors. The resulting power vectors can be used in a circuit simulation in evaluating (40) the power dissipation of a designed logic circuit.

Method of generating power vectors for cell power dissipation simulation

A clock network synthesis method and apparatus corrects for clock skew and impedance differences. A method includes identifying clock networks having more active elements as compared to other clock networks of a plurality of clock networks, for those identified clock networks, identifying a pattern of active elements therein as transversed by a clock signal, and for those unidentified clock networks in the correlated clock networks, adding active elements such that those added active elements transversed by the clock signal match those transversed in the identified clock networks. A method for preventing clock skew and impedance differences includes performing a clock balancing, identifying each related node across a sub-network, identifying each input driven via the identified related nodes, and adding one or more active elements to one or more nodes until each element in the identified related nodes drives a same number of inputs.

System and method for correlated clock networks

A method of generating power vectors to calculate power dissipation for a circuit is provided. The circuit includes both combinational logic and sequential logic circuits. The method includes removing all sequential logic circuits from the circuit. Boolean equations that describe the logical operation of the combinational logic of the circuit cells are generated. Power vectors are generated from the Boolean equations corresponding to internal and output transitions which dissipate power in the circuit. Redundant power vectors are then eliminated. The power vectors are then analyzed for "consistent" behavior with the sequential logic circuits. Operation of sequential logic circuits follow an ordered or defined sequence of events. Power vectors that are "inconsistent" with the operation of the sequential logic circuits are eliminated. The remaining power vectors are used to simulate the power dissipation of the circuit.

Alberto J. Reyes

Papers

Method of selecting device threshold voltages for high speed and low power

Low power flip-flop circuit and method thereof

Method of generating power vectors for cell power dissipation simulation

System and method for correlated clock networks

Method of generating power vectors for circuit power dissipation simulation having both combinational and sequential logic circuits