Showing papers by "Alberto Leon-Garcia published in 1994"

The helical switch: a multipath ATM switch which preserves cell sequence

Abstract: The paper presents a new cell switching architecture for ATM-based networks. The proposed helical switch is a multistage interconnection network which implements the self-routing technique with efficient buffer sharing. Although the switch may route cells along multiple paths, the connection-oriented mode required by the ATM-based network is supported. Cell sequence integrity is guaranteed by introducing a virtual helix which forces cells routed along different paths to proceed in order and fill the internal buffers uniformly. The performance of the helical switch is investigated under uniform and nonuniform traffic patterns. Unlike single-path multistage networks such as buffered banyan networks which can degrade significantly under nonuniform traffic, the helical switch is shown to be quite robust with respect to nonuniform traffic conditions. >

Performance of burst-level bandwidth reservation in ATM LANs

Abstract: The authors investigate burst-level bandwidth reservation schemes in ATM LANs and compare the performance of REQ/ACK and on-the-fly reservation schemes for a client-server model with a single ATM switch. To compare performance, they derive an analytical model for the mean burst transfer delay, blocking probability and throughput. They discuss the dependence of these performance parameters on the propagation delay-to-burst duration ratio and peak rate-to-link speed ratio. They show that, for moderate propagation delay-to-burst duration ratio, the on-the-fly scheme is more desirable since the REQ/ACK scheme has limited achievable throughput for fast reservation traffic due to unused bandwidth during the REQ-ACK cycle. Also, for a given burst length (in bits), the delay performance of REQ/ACK scheme is more sensitive to increase in the peak rate than the on-the-fly scheme. >

Separation principle of dynamic transmission and enqueueing priorities for real- and nonreal-time traffic in ATM multiplexers

Abstract: In order to efficiently utilize network resources while still providing satisfactory QoS to both real-time and nonreal-time applications, prioritizing these two types of traffic according to their service requirement becomes necessary. Several slot-oriented transmission priority schemes applicable to the output queue of ATM switches have been proposed. We studied the slot-oriented queueing disciplines that further involve the buffer management of the output queue of ATM switches. A fundamental principle called the separation principle is presented, which asserts that (1) the QoS (measured by the time-cumulative cell loss for each traffic class) region of the efficient disciplines (provide the best QoS tradeoff between the two types of traffic) can be divided into two mutually exclusive ones by the QoS of a special efficient discipline called R*; and (2) the efficient disciplines may involve either dynamic transmission priority or dynamic enqueueing priority but not both depending on which of the two mutually exclusive QoS regions is desired. The QoS region of less time-cumulative nonreal-time cell loss than R* is shown to be approximately linear in the space of time-cumulative cell loss vector when the real-time traffic is well regulated. The suboptimal but simple disciplines which are functions of only a small set of system parameters are also investigated to achieve less time-cumulative nonreal-time cell loss than R*. >

A merging network scheme that builds large sorting networks

Abstract: We present a new scheme for building large sorting networks. The scheme is recursive in the sense of indicating how to build a large sorting network from modules of smaller sorting and merging networks. The scheme involves a regular wiring pattern between modules. When the scheme is applied to 2/spl times/2 comparison elements, we obtain a new sorting network with a wiring pattern that has fewer cross-over points than Batcher's (1968) networks. When the scheme is applied to modules of a given size, for example 32/spl times/32 single-chip sorters, then we obtain a multi-chip implementation of larger sorting networks. Thus the scheme presented allows us to circumvent technology limitations that currently limit the size of sorters that are implementable.

A Frame-Oriented Queueing Control Policy for Real-and Non-Real-Time Traffic in ATM Switches

Abstract: The need to carry various real-time and non-real-time applications involving diverse traffic arrival pattern and a wide range of QoS requirements in ATM-based BISDN has spurred research activity on queueing control in ATM switches. Frame-oriented queueing policies have drawn much attention recently, which alleviates the high-speed processing requirement of the slot-oriented policies. In this paper, we propose a frame-oriented queueing control policy based on Golden-Ratio hashed slot assignment for real-time and non-real-time traffic in the output queue of ATM switches. The buffer is shared by the two types of traffic. The proposed policy updates the transmission schedule at every frame according to the buffer state instead of the arrival traffic pattern. The enqueueing priority assignment will also be updated at every frame or slot according to the transmission schedule of the current frame and the buffer state at the current frame or slot. Under the proposed policy, the minimum aggregate time-cumulative cell loss (subject to the system parameters) can always be guaranteed for any arrival traffic pattern. The system parameters need to be changed only when the traffic load and profile change (due to setup and tear-down of connections). To exploit the potential of the proposed policy, the performance of the theoretically optimal discipline R* is used to benchmark the performance of the proposed policy under a wide variety of cases.