Integrated circuits (ICs) must be robust to manufacturing variations. Circuit simulation at a set of worst case corners is a computationally efficient method for verifying the robustness of a design. This paper presents a new statistical methodology to determine the worst case corners for a set of circuit performances. The proposed methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surfaces are then used to extract the worst case corners in the process parameter space as the points where the circuit performances are at their minimum/maximum values corresponding to a specified tolerance level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. The novel concept of a relaxation coefficient to ensure that the corners capture the minimum/maximum values of all the circuit performances at the desired tolerance level is also introduced. The corners are realistic since they are derived from the multivariate statistical distribution of the process parameters at the desired tolerance level. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/radio frequency (RF) blocks found in typical communication ICs.

Application-specific worst case corners using response surfaces and statistical models

Integrated circuits have to be robust to manufacturing variations This paper presents a new statistical methodology to determine the worst-case corners for a set of circuit performances Our methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions These response surface models are then used to extract the worst-case corners in the process parameter space as the points where the circuit performances are at their min/max values corresponding to a specified statistical level Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification We introduce the novel concept of relaxation coefficient to ensure that the corners capture the min/max values of all the circuit performances at the desired statistical level The corners are realistic since they track the multivariate statistical distribution of the process parameters Expected worst-case circuit performances can thus be extracted with a small number of simulations suitable for subsequent design verifications The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/RF blocks found in typical communication ICs

Application specific worst case corners using response surfaces and statistical models

Published research on path delay fault (PDF) testing has largely focused on the PDF classification and test-vector generation problems. Little attention has been paid to the diagnosis of delay faults and in defining realistic metrics for delay-fault coverage, We present a statistical diagnosis framework to detect which parts of the circuit are likely to have caused a chip failure for a set of delay-fault tests. Under a model where distributed fabrication-process perturbations contribute to the occurrence of delay faults, we also find the associated likely fabrication-process parameter deviations from their nominal values as part of the diagnosis framework. We present results of experiments performed on some International Symposium on Circuits and Systems 1989 (ISCAS'89) benchmark circuits and also relate the slack of a path segment to its probability of contributing to the circuit failure. We also quantify the diagnosability of a PDF for a test and develop a methodology based on our statistical diagnosis framework to determine the diagnosability of each PDF detected by a given test set. We apply this approach to find the diagnosability of robust PDFs for the ISCAS'89 benchmark circuits. Furthermore, we propose a new and realistic definition of delay-fault coverage based on the percentage of fabricated faulty chips that can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay-fault sizes caused by the chip manufacturing process as opposed to previously defined metrics that have been based primarily on the percentage of faults tested. We present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of PDFs caused by distributed fabrication-process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between PDF coverage estimates for robust test sets obtained using our realistic definition and the ones obtained by using the traditional notion of coverage as the percentage of paths tested.

Path delay fault diagnosis and coverage-a metric and an estimation technique

The impact of process fluctuations on the variability of deep sub-micron (DSM) VLSI circuit performances is investigated in this paper. In particular, we show that, as process dimensions scale down in the sub half-micron region, the relative weight of process variability tends to increase, thus wearing down a nonnegligible portion of the benefits that are expected from minimum feature size scaling. Therefore, in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as in the assigned probability technique (APT) (Dal Fabbro et al, Proc. 32nd ACM/IEEE Design Automation Conf., pp. 702-6, 1995). The application of the APT technique to a 16-bit ripple-carry adder designed in 0.35 /spl mu/m, 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies with a power supply ranging from 3.3 V down to 1 V demonstrates how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high performance or low-power systems in 0.18 /spl mu/m and lesser technologies.

Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep sub-micron CMOS technologies

Purpose – Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.Design/methodology/approach – The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.Findings – Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and h...

Effects of process variation in VLSI interconnects – a technical review

The possibility of determining the accurate worstcase timing performance of a library of standard cells is of great importance in a modern VLSI structured semicustom IC design flow. The margin for profitability is indeed extremely tight because of the ever increasing performance demand which can hardly be satisfied by a corresponding progress of the process technology. It is therefore of utmost importance to avoid excessively pessimistic estimates of the actual cell performance in order to exploit all the potential of the fabrication process. In this paper it is described a technique that allows to determine the worst-case points with an assigned probability value. It is thus possible to select the desired level of confidence for the worst-case evaluation of digital IC designs with good accuracy. The results of the Assigned Probability Technique (APT) are presented and compared with those obtained by standard methods both at cell and at circuit level showing the considerable benefits of the new method.

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Alessandro Dal Fabbro

Papers

An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard cells