Advanced packaging

Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.

Power distribution system design methodology and capacitor selection for modern CMOS technology

As microprocessor architectures continue to increase computing performance under low-energy consumption, the combination of signal integrity, electromagnetic interference, and power delivery (PD) is becoming crucial in the computer industry. In that context, PD engineers make use of complex and computationally expensive models that impose time-consuming industrial practices to reach an adequate PD design. In this article, we propose a general surrogate-based methodology for fast and reliable analysis and design optimization of PD networks (PDN). We first formulate a generic surrogate model methodology exploiting passive lumped models optimized by parameter extraction to fit PDN impedance profiles. This PDN modeling formulation is illustrated with industrial laboratory measurements of a fourth generation server CPU motherboard. We next propose a black box PDN surrogate modeling methodology for efficient and reliable PD design optimization. To build our black box PDN surrogate, we compare four metamodeling techniques: support vector machines, polynomial surrogate modeling, generalized regression neural networks, and Kriging. The resultant best metamodel is then used to enable fast and accurate optimization of the PDN performance. Two examples validate our surrogate-based optimization approach: a voltage regulator (VR) with dual power rail remote sensing intended for communications and storage applications, by finding optimal sensing resistors and loading conditions; and a multiphase VR from a fifth-generation Intel server motherboard, by finding optimal compensation settings to reduce the number of bulk capacitors without losing CPU performance.

Surrogate-Based Analysis and Design Optimization of Power Delivery Networks

This paper proposes methods for the modeling and analysis of signal integrity (SI) and radiated emission (RE) of capacitively loaded printed circuit board interconnections. Two techniques are considered for achieving a high level of SI, namely, source series damping and destination parallel damping. Low-order models are developed for the two methods, which enable a comparison of their SI performance and the identification of the key parameters that affect SI. Under certain conditions, the two methods are shown to have approximately the same SI performance. However, the two techniques can exhibit different characteristics in other respects, such as power dissipation, peak current, and RE. One particular characteristic that is studied in this paper is the performance with respect to far-field REs. A key objective of this paper is to develop a quantitative analysis and a qualitative understanding of the interplay between electromagnetic compatibility-electromagnetic interference and SI for the two damping techniques.

Modeling and Analysis of Radiated Emissions and Signal Integrity of Capacitively Loaded Printed Circuit Board Interconnections

A key aspect of power integrity in modern electronic systems is the choice and optimization of decoupling capacitors. Traditionally, this issue has been addressed at PCB level, but the integration of discrete SMD capacitors inside BGA package substrates is becoming more and more common in complex high-speed digital devices. In the context of semiconductors industry, the on-package decoupling applied to digital microcontrollers needs to be defined, often without any clear information on system configuration. This paper shows how the package behavior can change depending on the interaction with PCB parameters, and proposes a methodology to optimize on-package decoupling taking into account the system variability.

Optimization of on-package decoupling capacitors considering system variables

A complete simulation methodology for the design of optimized Power Delivery Network dedicated to High Speed High Density electronic board is presented in this paper. Each part of the Power Supply Circuit is modeled either in the time domain or in the frequency domain with the adequate tools available on the market, and these models are correlated with measurement results thanks to a dedicated test vehicle. The article focuses particularly in the design process of the Power Delivery Network from the point of view of a Printed Circuit Board Designer with very few information on the internal design of the components constituting the design, like monolithic DC-DC converter or Complex Ball Grid Array integrated circuit. Thus, the presented methodology takes into account the behavior of the Integrated Circuit obtained by measurement. Settings for Integrated Circuit characterization are precisely described and measurement limitations are commented. Finally the validity of the whole simulation is checked through comparisons with measurements in the frequency domain.

Power Delivery Network simulation methodology including Integrated Circuit behavior

This study presents the use of a design flow and remarkable results of signal integrity crosstalk simulations of Multi-GigaHertz serial links in high density printed circuit boards, which becomes mandatory due to increase of data rates

Crosstalk analysis of multigigabit links on high density interconnects PCB using IBIS AMI models

Embedded electronics merge always more and more enhanced functionalities, which implies that the printed circuit boards (PCB) need to achieve higher integration levels. Furthermore, signal integrity must be ensured, and the increasing use of multi-gigabits serial links requires a detailed analysis of the electrical behavior of tracks and vias for frequencies up beyond 10MHz. Thus, the different stack-up are enhanced in order to satisfy data rate beyond 10 Gbps. This paper relies on stacked microvias, which are a very innovative technology permitting a better level of integration compared to usual microvias or through hole vias. Indeed, they have a very good electrical behavior on a large frequency range (DC to 18 GHz) contrary to classical through hole via where possible stub effects deteriorate signal integrity. Moreover, it is easier to optimize the stacked microvia structure compared to standard microvias. Electrical characterization of these vias structures are evaluated through measurement on test vehicles and 3D modelling using CST Microwave Suite.

Electrical behavior of stacked microvias integration technologies for multi-gigabits applications using 3D simulation

In this paper, a detailed power integrity study is described that compares the behavior of surface-mount devices and embedded components for power decoupling. Through measurements and simulations, it is found that when the layer count of the board is low, there is no significant difference between both technologies. When the number of layers increases, the short connection for the embedded components is clearly superior to the surface-mount capacitor. The resonance frequencies for the embedded capacitor do not change significantly with the increased layer count. The case with the surface-mount capacitor however, shows a large increase in parasitic inductance due to the long vias through the board.

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Embedded passive components for improved power plane decoupling

In this article, different patterns for decoupling capacitor routed on a dedicated test vehicle are compared. The aim of this study is, on one hand to confirm design rules for enhanced decoupling on printed circuit board and on the other hand, to estimate the value of the mounted inductance introduced by each pattern. Each mounting pattern and the particular parameter which is studied for each case will be described and measurement methodology as mounted inductance calculation will be presented. Then, mounted inductance calculated from measurement and results given by simulation are compared in order to see the precision reached by recent hybrid EM solver dedicated to Printed Circuit Board for parasitic elements calculation. Finally design rules and trade off for better decoupling are given as a conclusion.

Alexandre Amedeo

Papers

Power Delivery Network simulation methodology including Integrated Circuit behavior

Crosstalk analysis of multigigabit links on high density interconnects PCB using IBIS AMI models

Electrical behavior of stacked microvias integration technologies for multi-gigabits applications using 3D simulation

Embedded passive components for improved power plane decoupling

Evaluation and comparison of mounted inductance for decoupling capacitor