A family of bandgap embodiments are disclosed herein, capable of operating with very low currents and low power supply voltages, using neither any custom devices nor any special manufacturing technology, and fabricated on mainstream standard digital CMOS processes. As such, manufacturing cost can be kept low, manufacturing yields of digital CMOS system-on-a-chip (SOC) that require a reference can be kept optimal, and manufacturing risk can be minimized due to its flexibility with respect to fabrication process node-portability. Although the embodiments disclosed herein use novel techniques to achieve accurate operations with low power and low voltage, this family of bandgaps also uses parasitic bipolar junction transistors (BJT) available in low cost digital CMOS process to generate proportional and complementary to absolute temperature (PTAT and CTAT) voltages via the base-emitter voltage (V EB ) of BJTs and scaling V EB differential pairs to generate the BJTs thermal voltage (V T ).

Ultra-low power and ultra-low voltage bandgap voltage regulator device and method thereof

An input-output rail-to-rail buffer amplifier is presented that is low noise, fast, and operates at ultra low currents. The amplifier targets energy harvesting applications that require low cost, high volume, and rugged manufacturing by avoiding use of non-standard device configurations or special processes. The main contributions of this work are: (1) The method of lowering voltage output noise by narrow-banding an amplifier, while introducing a time dependent bias current boost that is triggered by large differential input signals. Narrowbanding an amplifier to reduce its output noise, slows its dynamic response, and this method aims to restore and boost both the amplifier's slew rate and settling time. (2) Amplifier can operate at low VDD of about VGS+2VDS, while running in subthreshold, based in standard 0.18u digital CMOS. (3) PMOSFETs are utilized as inputs, compensation capacitors, and bias resistors in both the amplifier and the boost stages, which helps optimize for yield and lower noise. More importantly, the dynamic response of both the main amplifier and the boost stage being substantially dependent on PMOSFET device parameters, facilitates a smoother dynamic response in and out of boost, over process and operating variations. Based on montecarlo (MC) and worst case (WC) simulations, the following specifications are achievable: voltage output noise (VO nOiSe ) of 10 uv/Hz⁁1/2 at 1KHz, supply current (Idd) ∼ 500 nA; V dd minimum ∼0.6V; rail-to-rail voltage input (V IN ) range and output voltage (V OUT ) range of ∼ +/− 25mv from the rails; output resistor load (R l ) ∼2k Ohms; output capacitor load (C l ) ∼1nF; slew-rate (SR) −/+ ∼ 4/2.5 v/us; settling time (t S ) ∼ 5us to 1%; power supply rejection ratio (PSRR) −/+ ∼ 80dB/85dB, common mode rejection ration (CMRR) ∼ 125dB, unity gain bandwidth (f r ) ∼ 20KHz with phase margin (PM) ∼ 75 degrees; open loop gain (G) ∼ 85dB; preliminary area estimate of ∼ 180 um per side.

Low noise rail-to-rail amplifier runs fast at ultra low currents and targets energy harvesting

Targeting the energy harvesting applications that require multiple channels of matched buffer amplifiers on a chip, a small rail-to-rail input-output, ultra low current, and low supply voltage (VDD) buffer amplifier is presented. The contributions of this work are as follows: First, an output buffer driver utilizes a loser-take-all circuit (LTA) and a current mirror amplifier (CMA) circuit to regulate the current in either of the inactive sink or source output driver transistors (FET). In conjunction with the LTA and CMA, a complementary noninverting current mirror (CNICM), monitors and rectifies the sink-source output signals before they are fed to the LTA circuit. Hence, the amplifier's current consumption, attributed to monitoring external loads, is substantially curbed. More importantly, because all the elements of the buffer driver (LTA, CMA, and CNICM) operate mainly in current mode, the output buffer driver is structurally fast and can operate with low V DD of about V GS +2V DS . Second, a floating current source (FCS) function is emulated that can also operate with low VDD and is fast in lieu of utilizing auxiliary common gate amplifiers (CGA). The FCS contains two complementary cascoded FET current sources where the middle cascoded FET's VGSs are held constant and their drain currents are criss-crossed and fed to each other's source terminals, while CGAs regulate the V GS s of the lower FETs, whose currents are substantially equalized and mirrored into the Amplifier's bias network. Montecarlo (MC) and worst case (WC) simulations indicate the following specifications are achievable: V DD minimum ∼ 0.8v; I DD ∼ 200nA; input voltage range rail to rail; output voltage range ∼ 10mV from the rails; open loop gain (A V ) ∼ 115dB with unity gain bandwidth (f U ) ∼ 600KHz and phase margin (PM) ∼ 30 degrees; power supply rejection ratio (PSRR) ∼ − 88dB; common mode rejection ratio (CMRR) ∼ − 120dB; slew rate (SR) ∼ 2V/ 5uS; settling time (t S ) ∼ 10uS; output resistor (R L ) capability ∼10K Ohms; and die size rough estimate is 100 um per side.

Compact ultra low power class AB buffer amplifier

A CMOS subthreshold rail-to-rail input-output buffer amplifier suitable for energy harvesting applications is presented, having high gain (A V ) of ∼ 130dB, consuming ultra low currents (I DD ) of ∼ 150nA, and operating with low power supply voltage (V DD ) > ∼ 0.8v. Contributions of this work are the synthesis of the following attributes: First, using a single transistor, the amplifier input stage's tail current is steered between the two PMOSFET input pairs, while one of the PMOSFET pairs is level shifted by a pair of NMOSFET source followers, which keeps the amplifier's input stage transconductance (gm) roughly constant while the inputs span rail-to-rail. Second, to boost folded cascode transconductance amplifier's (FCTA) A V , the proposed plurality of regulated cascode (RGC) current mirrors (CM) utilize a small size auxiliary amplifier, containing the same type and un-scaled FETs as that of the cascoded CMs employed within the FCTA. As such, the boosting of AV is less impeded by the otherwise higher impedance and high capacitance associated with scaled FETs, utilized in most prior art, in the RGC's auxiliary amplifier's signal path. Moreover, the RGC-CM utilizing the same FET, as that of the FCTA's CM, provides more consistency in FCTA's DC, AC, and dynamic response over process and operating condition variations. Third, a buffer driver containing a Minimum Current Selector (MCS) and an inverting current mirror amplifier (ICMA) controls the quiescent current of the inactive output transistors (FETs), while a complementary noninverting current mirror (CNICM) curbs the current waste attributed to monitoring the FET's (external load) currents. The output buffer driver is inherently fast and can work at low VDD, since it operates mainly in current mode. Montecarlo (MC) and worst case (WC) simulations indicate the following specifications are achievable: input voltage range rail to rail; output voltage range ∼ 10mV from the rails; resistive load (RL) 5K ohms capability; unity gain frequency (fu) ∼ 200KHz and phase margin (PM) ∼ 40 degrees; power supply rejection ratio (PSRR) ∼ −90dB; common mode rejection ratio (CMRR) ∼ −110dB; slew rate (SR) ∼ 3V/ 10uS; settling time (ts) ∼ 15uS; size ∼130um/side.

Enhanced gain, low voltage, rail-to-rail buffer amplifier suitable for energy harvesting

Methods, circuits, and apparatuses are disclosed that provide a buffer amplifier with lower output noise by narrow banding the amplifier. To reinvigorate the speed of the narrow-banded amplifier, a boost-on signal is initiated. The boost-on signal dynamically and rapidly injects a substantial current into the amplifier's bias current network to speed up its slew rate, when the amplifier's inputs get unbalanced when being subjected to a large transient differential input signal. Subsequently, after the amplifier regulate itself and as the amplifier's inputs approach substantial balance, a boost-off signal dynamically injects a slow and decaying current (that converges to the level of static steady-state bias current) into amplifier's bias circuitry, instead of turning off the boost current rapidly, which improves the amplifier's settling time.

Low noise amplifier running fast at ultra low currents

A bias current topology with embodiments in current source, current reference, (pseudo bandgap) voltage reference, and bandgap voltage reference that operate at ultra low currents and low power supply voltages which may use main stream standard digital Complementary Metal-Oxide-Semiconductor (CMOS) processes. The bias current topology uses chiefly a self cascode (SC), whose active resistor MOSFET is paced in series with the gate input of the MOSFETs that help generate the proportional to absolute temperature (PTAT) voltage that is applied to the active resistor MOSFET to produce a bias current.

Ali Tasdighi Far

Papers

Ultra-low power bias current generation and utilization in current and voltage source and regulator devices