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Alireza Kasnavi
Researcher at Synopsys
Publications - 13
Citations - 156
Alireza Kasnavi is an academic researcher from Synopsys. The author has contributed to research in topics: Integrated circuit & Delay calculation. The author has an hindex of 5, co-authored 13 publications receiving 155 citations.
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Patent
Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques
TL;DR: In this paper, the effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation.
Patent
Determining a design attribute by estimation and by calibration of estimated value
TL;DR: In this paper, a computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (eg nominal values of channel length or metal width), to obtain at least a first value of the attribute.
Patent
Determining equivalent waveforms for distorted waveforms
TL;DR: In this paper, an equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated by calculating the transition quantity of a first non-distorted waveform.
Proceedings ArticleDOI
Noise library characterization for large capacity static noise analysis tools
TL;DR: A characterization methodology is developed to generate noise immunity criteria (NIC) and noise propagation tables (NPT) for a given cell library and the resulting look-up tables are appended to any standard gate-level library to be utilized by static timing and noise analysis tools.
Proceedings ArticleDOI
Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop
TL;DR: A new technique is proposed that eliminates the clock sweeping by using the meta-stable point of sequential cells, which is on average 58times faster than the conventional clock sweeping method and its average error is only 2.4%.