Showing papers by "Alistair McEwan published in 2004"

A low power high speed accumulator for DDFS applications

Abstract: An accumulator optimised for use in a Direct Digital Frequency Synthesis (DDFS) system with 24 bits of frequency resolution and 13 bits of phase resolution is presented. Update rates in excess of 800 MHz are achieved by careful choice of architecture. Power dissipation is lowered by removing redundant circuitry. The static, D-type flip flops used in the pipeline architecture are the dominant source of power dissipation. Hence the refresh-every-cycle operation of accumulators in DDFS is exploited by using dynamic delay elements to reduce power consumption.

An alternative analog VLSI implementation of the Meddis inner hair cell model

Abstract: A circuit implementation of a model of the inner hair cell based on the Meddis inner hair cell model is presented. The model and implementation are alternatives of a previously presented exact implementation of the Meddis hair cell model. Models of the IHC are becoming more computationally intensive and require substantial analogue circuits to allow full implementation. The alternative model is more compact, less complex and more biologically plausible. The current mode circuit uses a modified differential pair input stage, translinear multiplier and translinear first order low pass filters to create large time constants with small capacitors.