A method of formal transformation of a multidimensional DFT (discrete Fourier transform) algorithm to a form suitable for implementation with a systolic macropipeline is discussed. The suggested transformation of the original form of the DFT algorithm consists of one or several rotationlike transforms applied to the index set. The resulting 'completely systolized' form of the algorithm makes it possible to implement the N/sup M/-point (m-dimensional) DFT with a macropipeline containing M or (M-1) cascaded systolic/semisystolic arrays. Each array is an M-dimensional hypercube of the processing elements (PEs) of the multiply-add type; the internal structure of PEs in different arrays is slightly different. For given values of N and M, several design options exist, with hardware complexity of about the same value. The proposed systolic architecture makes it possible to obtain the throughput of N (one set of spectrum values every N array clocks) for any number of dimensions M. >

Multidimensional Fourier transforms by systolic architectures

A generalized architecture is presented for reconfigurable m-ary tree structures, where m is any integer >1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors previously (1990) for obtaining reconfigurable binary tree structures. The generalized architecture with m/sup k/ processing elements or nodes (where k is any integer >1) is implemented with a k-stage MIN. A single control code issued to the MIN establishes a distinct m-ary tree configuration among the nodes. The favorable features of the architecture include fast reconfiguration, simplified hardware in the nodes and the MIN, and simple routing control. The reconfigurability of the architecture is proved, and the results of the analysis are utilized to provide a procedure to synthesize the m-ary tree configuration that is generated for any given control code. Considerations for implementing the switching elements of the MIN are discussed. >

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Design and analysis of a generalized architecture for reconfigurable m-ary tree structures

An architecture called the generalized multiple bus-connected parallel computer (GMBPC) is studied. The GMBPC is suitable for optical interconnection and wafer-scale packaging applications and operates as a message-passing multiple-instruction multiple-data (MIMD) machine in this investigation. The performance of the GMBPC is modeled by generalized stochastic Petri nets (GSPNs). To lessen the exponential distribution assumption used in the GSPN model, a Monte Carlo simulation technique is used to predict the performance probabilistically. For application, two dimensional fast Fourier transform algorithms for the GMBPC are derived. The GMBPC's performance in solving the multidimensional Poisson's equation using relaxation and fast Fourier transform methods with different parameters and problem sizes is analyzed. >

A Study of the Generalized Multiple Bus-Connected Parallel Computer.

A Study of the Generalized Hultiple Bus-Connected Parallel Computer

A very high throughput signal processor is shown to be capable of generating medium resolution SAR spotlight images at faster than real time rates (i.e., faster than the airborne SAR sensor is able to gather the data to be processed). Also described is a method that uses the available processing power to achieve enhanced look-down detection sensitivity for ground or airborne targets that are moving slowly in range. The technique described is intended for use in combination with classical main beam clutter cancellation or nulling techniques such as Arrested Displaced Phase Center Antema (ADPCA). The highly parallel multi-processor is programmable in the "C" high level language and is scalable from a minimum throughput of 400 MFLOPS to a maximum of 3.2 GFLOPS. The modular design, flexible topology and redundant interconnectivity between Processing Elements results in a highly fault tolerant architecture. Advanced 3-D packaging of the multi-processor offers the prospect of an 800 MFLOP array implemented for avionic applications in a volume of 9 cubic inches.

Allen L. Gorin

Papers

Computing the Two-Dimensional Discrete Fourier Transform on the ASPEN Parallel Computer Architecture.