(1991). Applied Linear Regression Models. Journal of Quality Technology: Vol. 23, No. 1, pp. 76-77.

Applied Linear Regression Models

A flow is presented for the automatic synthesis of an analog circuit layout based on a schematic and a list of circuit design parameter values. The flow is driven by design, placement, and routing constraints-no layout template is necessary. Every possible layout for each device in the circuit is investigated; the layouts with the best geometric features and smallest quantization error (due to manufacturing grid alignment) are kept. For circuit placement, a complete enumeration of possible circuit placements, limited only by usual constraints of symmetry, proximity, and common centroid, is performed. Out of this enumeration a final circuit placement is selected and routed. The new flow is integrated with a deterministic nonlinear optimization algorithm to perform layout-driven circuit sizing; layouts are synthesized during both gradient approximation and next step determination. Layout-driven circuit sizing was applied to two example circuits. Sizing of the first circuit example took 8× the amount of CPU time needed for traditional circuit sizing, but remained feasible at 2.1 h of wall clock time on a contemporary workstation.

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Constraint-Based Layout-Driven Sizing of Analog Circuits

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

The design of analog integrated circuits (ICs) is characterized by time-consuming and non-systematic iterations between electrical and physical design steps in order to achieve successful post-layout designs. This paper presents an innovative methodology for automatic optimization-based sizing of analog ICs that takes into consideration complete layout-related data for both circuit's geometric requirements, which are obtained from the real-time in-loop floorplan packing, and circuits' electrical performance that is evaluated using circuit simulator and considering accurate layout parasitic estimates. In order to boost the parasitic extraction efficiency, the need for expensive detailed layout generation, as found in previous state-of-the-art layout-aware sizing approaches, is here circumvented. However, the interconnect parasitic capacitances that are major contributors to performance degradation and on-die signal integrity problems, must be accurately accounted for. Therefore, an empirical-based parasitic extraction is performed on an early-stage layout obtained from the floorplan, computing the optimal electromigration-aware wiring topology and shortest rectilinear paths in-loop, without the need for detailed routing. Finally, the methodology is demonstrated for the UMC 130nm design process using well-known analog building blocks proving the generality, accuracy and fast execution of the proposed approach.

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction

Floorplan-aware analog IC sizing and optimization based on topological constraints

Accurate and fast optimization of analog circuits is an important requirement of current synthesis methods. Obtaining the entire pareto optimal surface for conflicting performance objectives is essential for design space exploration as well as circuit sizing. Layout parasitics prevent the circuit from realizing the estimated optimal performance values but are not considered in most existing pareto-front generation methods. We develop a layout-aware circuit matrix modeling method along with an efficient multi-objective optimizer to synthesize the parasitic inclusive pareto-optimal performance surface. The algorithm achieves a pareto surface with points spread uniformly in all regions. The sensitivity of critical performance to candidate design points is used to select the best sizing solution during synthesis. Experiments on benchmark circuits show the effectiveness of the proposed method in obtaining a speedup of an order of 10$^{3}$ with negligible loss of accuracy as compared to SPICE.

Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits

Automated analog circuit synthesis techniques depend on fast and reliable estimation of circuit performance. This paper presents a highly accurate method of estimating performances by constructing models of the circuit matrix instead of the traditionally used performance models. Device matching in analog circuits is utilized to identify identical elements in the circuit matrix and reduce the number of elements to be modeled. Experiments conducted on three operational amplifier topologies demonstrate the effectiveness of the method in achieving correct performance prediction. Results show that the performances can be predicted within a mean error of 0.1% compared to a SPICE simulation.

Regression based circuit matrix models for accurate performance estimation of analog circuits

We propose an algorithm for sizing analog circuits using parasitic aware circuit matrix models. A novel scheme of separating schematic and parasitic models is proposed. As layout details are not abstracted in the circuit performance, the developed models can be used for different module geometries. Regression models developed make parasitic estimation much faster than a layout inclusive approach. The proposed approach is successfully used for dynamic module geometry selection during synthesis. Experiments conducted on operational amplifier and filter topologies demonstrate the accuracy of our proposed approach. For both circuits, results are within a mean error of 1 percent compared to an exact layout and spice approach.

A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection

Achieving accurate and speedy circuit sizing is a challenge in automated analog synthesis. System matrix model based estimators predict circuit performance accurately. In this paper we employ hashing in conjunction with matrix models for faster synthesis convergence. With hash tables some matrix element recomputations are avoided, thus improving synthesis time. Hashing is effectively performed by dividing matrix elements into classes and building class-wise hash tables. Hash tables are updated over several synthesis runs which further expedites convergence. Experimental results show that the proposed method can provide 4x-6x speedup over that offered by synthesis approaches employing macromodels but no hashing.

On the Use of Hash Tables for Efficient Analog Circuit Synthesis

We present an efficient analog synthesis algorithm employing regression models of circuit matrices. Circuit matrix models achieve accurate and speedy synthesis of analog circuits. In this paper, synthesis is accelerated by eliminating numerous computations of the matrix elements during a synthesis run. Computations are avoided by reusing exact or nearby design points visited during previous synthesis iterations. Hashing and multidimensional nearest neighbor lookup are used in incremental evaluation of design solutions encountered during synthesis. Sensitivity of the design variables is considered for locating a neighboring solution. Neighbor lookup is efficiently performed using box-decomposition trees. The proposed method is used to synthesize three benchmark circuits. Results show that with hashing and neighbor lookup, synthesis is 6x--13x faster than with the use of matrix models alone.

http://www.cecs.uci.edu/~papers/date08/PAPERS/2008/DATE08/PDFFILES/IP2_4.PDF

Almitra Pradhan

Papers

Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits

Regression based circuit matrix models for accurate performance estimation of analog circuits

A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection

On the Use of Hash Tables for Efficient Analog Circuit Synthesis

Fast analog circuit synthesis using sensitivity based near neighbor searches