There can be little doubt that the Monte Carlo method for semiconductor device simulation has enormous power as a research tool. It represents a detailed physical model of the semiconductor material(s), and provides a high degree of insight into the microscopic transport processes. However, if the authority ascribed to Monte Carlo models of devices at 1/spl mu/m feature size is to be maintained for devices below O.1/spl mu/m, modelling of the fundamental physics must be further improved. And if the Monte Carlo method is to be successful as a semiconductor device design tool, the device model must be made more realistic. Success in the industrial sector depends on this, but also on achieving fast run-times optimisation - where the scope and need for ingenuity is now greatest.

The Monte Carlo method for semiconductor device simulation

In one aspect there is provided a method. The method may include receiving a first analog radio frequency signal including a signal of interest and an interference signal caused by a second analog radio frequency signal transmitted in full duplex over a channel from which the first analog transmission is received; combining the first analog radio frequency signal and a portion of the second analog radio frequency signal to generate an output analog radio frequency signal characterized by at least a reduction or an elimination of the interference signal included in the output analog radio frequency signal; and providing the output analog radio frequency signal. Related apparatus, systems, methods, and articles are also described.

Single channel full duplex wireless communications

Aspects and features are directed to an uplink integrity detection sub-system. In one aspect, a distributed antenna system is provided that includes a remote antenna unit that communicates with wireless devices in a coverage area, additional remote antenna units that communicate with wireless devices in additional coverage areas, and a unit that communicates with the remote antenna unit and the additional remote antenna units. The unit includes a distributed antenna system controller. The distributed antenna system controller can determine that an undesirable signal component having a power level exceeding a threshold power is communicated via an uplink path from the remote antenna unit. The distributed antenna system controller can also minimize an impact of the undesirable signal component on the additional coverage areas of the additional remote antenna units. Minimizing the impact can include modifying the gain of the uplink path over which the undesirable signal component is communicated.

Uplink path integrity detection in distributed antenna systems

Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin s...

Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

We investigate a Magnetic Josephson Junction (MJJ) - a superconducting device with ferromagnetic barrier for a scalable high-density cryogenic memory compatible with energy-efficient single flux quantum (SFQ) circuits. The superconductor-insulator-superconductor-ferromagnet-superconductor (SIS'FS) MJJs are analyzed both experimentally and theoretically. We found that the properties of SIS'FS junctions fall into two distinct classes based on the thickness of S' layer. We fabricate Nb-Al/AlOx-Nb-PdFe-Nb SIS'FS MJJs using a co-processing approach with a combination of HYPRES and ISSP fabrication processes. The resultant SIS 'FS structure with thin superconducting S'-layer is substantially affected by the ferromagnetic layer as a whole. We fabricate these type of junctions to reach the device compatibility with conventional SIS junctions used for superconducting SFQ electronics to ensure a seamless integration of MJJ-based circuits and SIS JJ-based ultra-fast digital SFQ circuits. We report experimental results for MJJs, demonstrating their applicability for superconducting memory and digital circuits. These MJJs exhibit IcRn product only ~ 30% lower than that of conventional SIS junctions co-produced in the same fabrication. Analytical calculations for these SIS 'FS structures are in a good agreement with the experiment. We discuss application of MJJ devices for memory and programmable logic circuits.

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

A system and method for receiving a signal, comprising an input adapted to receive a radio frequency signal having a strong interferer; a signal generator, adapted to produce a representation of the interferer as an analog signal generated based on an oversampled digital representation thereof; and a component adapted to cancel the strong interferer from radio frequency signal based on the generated analog signal to produce a modified radio frequency signal substantially absent the interferer. The system typically has a nonlinear component that either saturates or produces distortion from the strong interferer, which is thereby reduced. The system preferably employs high speed circuits which digitize and process radio frequency signals without analog mixers.

System and method for digital interference cancellation

A radio frequency receiver subject to a large in-band interferor employs active cancellation with coarse and at least one cancellation signals, each with a respective radio frequency combiner, in order to increase the effective dynamic range of the receiver for weak signals of interest. One or both can be digitally synthesized. This is particularly applicable for co-site interference, whereby the interfering transmit signal is directly accessible. A similar system and method may also be applied to external interferors such as those produced by deliberate or unintentional jamming signals, or by strong multipath signals. An adaptive algorithm may be used for dynamic delay and gain matching. In a preferred embodiment, a hybrid technology hybrid temperature system incorporates both superconducting and semiconducting components to achieve enhanced broadband performance.

Two stage radio frequency interference cancellation system and method

HYPRES has developed a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC uses the phase modulation-demodulation low-pass architecture and on-chip digital filtering. Detailed experimental results at 20 GHz clock frequency of the ADC chip fabricated with a 1 kA/cm2 Nb process are presented and discussed. In addition to the standard ADC configuration, different ADC modifications are described. In the multi-rate ADC, the modulator sampling frequency is the twice the clock frequency for the time-interleaved digital filter. In addition to the standard parallel-output ADC, a serial output ADC and its interface to room temperature electronics are developed. This serial ADC chip fabricated with the advanced HYPRES 4.5 kA/cm2 process operated up to 34 GHz clock. As a major step toward commercialization of superconducting electronics, an ADC chip was successfully packaged on a cryocooler where it showed reduced performance up to 11.52 GHz clock.

Superconducting High-Resolution Low-Pass Analog-to-Digital Converters

We address all round development of the standard cell library including simulation, layout, and testing. We present a new circuit analysis scheme based on Monte-Carlo simulations and process corners. Using a phase modulation decoder as an example circuit, we identify weak spots in the design that was originally optimized for parameter margins. To support static timing analysis for very high complexity circuits, we describe the timing characterization of library cells as a function of its load, and demonstrate digital timing verification with timing back-annotation using Verilog hardware descriptive language. For the layout of library cells, we present architecture for the dual RSFQ/ERSFQ standard cell library for the MIT-LL, 10 kA/cm2, SFQ4EE and SFQ5EE processes. Testing and characterizing hundreds of library cells, including unique cells and their layout variations, is a challenge. For efficient characterization of the digital cells, we have developed an NDRO cell-based multiplexing scheme that lets us characterize hundreds of cells on a single chip. For better model-to-hardware correlation, we have implemented a differential delay measurement scheme using ring oscillators that facilitates timing characterization of the synchronous and asynchronous cells. We also report design and measurement of statistical variations for the critical current of decision-making pair of junctions.

RSFQ/ERSFQ Cell Library With Improved Circuit Optimization, Timing Verification, and Test Characterization

A wide variety of applications, ranging from radio-frequency (RF) receivers for broadband communications and signal detection, on earth and in space, would benefit from high-performance superconductor analog-to-digital converters (ADCs), based on magnetic flux quantization and fast switching Josephson junctions. Superconductor ADCs are capable of very high sample rates (100 GHz or more), very high linearity, and high sensitivity. Nyquist-rate ADCs use the high sample rate to digitize a wide instantaneous bandwidth (tens of GHz) and are useful for wideband spectrum monitoring as well as high-end scientific instrumentation. Delta and delta-sigma oversampling ADCs use the high linearity to achieve programmable trade-off between dynamic range and instantaneous bandwidth. These lowpass and bandpass ADCs have been used for direct digitization of narrower (tens to hundreds of MHz) RF bands in the 1–20 GHz range for a variety of communications, intelligence, electronic warfare, and radar applications. Another application area of these cryogenic ADCs is for outputs of cryogenic sensor arrays and terahertz mixers. Recent advances in various classes of ADCs for different applications are described.

Amol Inamdar

Papers

System and method for digital interference cancellation

Two stage radio frequency interference cancellation system and method

Superconducting High-Resolution Low-Pass Analog-to-Digital Converters

RSFQ/ERSFQ Cell Library With Improved Circuit Optimization, Timing Verification, and Test Characterization

Superconductor analog-to-digital converters and their applications