In a previous work it was argued that by studying evolved designs of gradually increasing scale, one might be able to discern new, efficient, and generalisable principles of design. These ideas are tested in the context of designing digital circuits, particularly arithmetic circuits. This process of discovery is seen as a principle extraction loop in which the evolved data is analysed both phenotypically and genotypically by processes of data mining and landscape analysis. The information extracted is then fed back into the evolutionary algorithm to enhance its search capabilities and hence increase the likelihood of identifying new principles which explain how to build systems which are too large to evolve.

Principles in the Evolutionary Design of Digital Circuits—Part II

From the Publisher:
Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks.
An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries.
Switching Theory for Logic Synthesis is based on the author's lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies.
Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.

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Switching Theory for Logic Synthesis

Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose a hierarchical approach to verifying arithmetic circuits, here basic building blocks are first shown to implement a word-level specification. The overall circuit functionality is then verified at the word level. Multipliers with word sizes of up to 62 bits have been verified by this technique.

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Verification of Arithmetic Functions with Binary Moment Diagrams

Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as formal verification, logic synthesis, and test generation. OBDDs represent Boolean functions in a form that is both canonical and compact for many practical cases. They can be generated and manipulated by efficient graph algorithms. Researchers have found that many tasks can be expressed as series of operations on Boolean functions, making them candidates for OBDD-based methods. The success of OBDDs has inspired efforts to improve their efficiency and to expand their range of applicability. Techniques have been discovered to make the representation more compact and to represent other classes of functions. This has led to improved performance on existing OBDD applications, as well as enabled new classes of problems to be solved. This paper provides an overview of the state of the art in graph-based function representations. We focus on several recent advances of particular importance for formal verification and other CAD applications.

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Binary decision diagrams and beyond: enabling technologies for formal verification

An efficient package for construction of and operation on ordered Kronecker Functional Decision Diagrams (OKFDD) is presented. OKFDDs are a generalization of OBDDs and OFDDs and as such provide a more compact representation of the functions than either of the two decision diagrams. In this paper basic properties of OKFDDs and their efficient representation and manipulation are presented. Based on the comparison of the three decision diagrams for several benchmark functions, a 25% improve ment in size over OBDDs is observed for OKFDDs.

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams

The authors introduce fast exact and quasi-minimal algorithms for minimal fixed polarity AND/XOR canonical representation of Boolean functions. The method uses features of arrays of disjoint cubes representations of functions to identify the minimal networks. These features can drastically reduce the search space and provide high quality heuristics for quasi-minimal representations. Experimental results show that these special AND/XOR networks, on the average, have a similar number of terms to Boolean AND/OR networks while there were functions for which AND/XOR circuits were much smaller. The circuits generated are much more testable. >

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Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks

This paper introduces a new design approach that combines logic and layout synthesis for Cellular-Architecture (CA) FPGAs. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and produces a rectangularly-shaped multi-level structure of (mostly) locally connected cells. This two-dimensional array of logic cells is well suited for CA-type FPGA realization. Two stages: restricted factorization and technology folding are discussed in more details. The architecture constraints and the implementation are presented for ATMEL6000 series architecture.

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A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays

A quasi-minimal algorithm for canonical restricted mixed polarity (CRMP) AND/XOR forms is presented. These forms, which include the consistent and inconsistent generalized Reed-Muller (GRM) forms, are both very easily testable and, on average, have smaller numbers of terms than sum-of-product (SOP) expressions. The set of test vectors for detecting stuck-at and bridging faults of a function realized in CRMP forms, like that of consistent (GRM) forms, is independent of the function. This test can be of order (n+4)r, where n is the number of variables in the function and r is the number of component consistent GRMs in the CRMP. The experimental results confirm the compactness of CRMPs as compared to SOP expressions. >

Fast minimization of mixed-polarity AND/XOR canonical networks

A description is presented of the high-level and logic synthesis stages in the digital design automation system DIADES. High level design, namely, data path synthesis, and control unit synthesis start from a parallel program graph, the form of description that includes both the control-flow and the data-flow graph. While the data path is allocated and scheduled, the control unit is designed to be composed of either microprogrammed units or finite-state machines. The latter are minimized in two dimensions (states and inputs), assigned and realized in logic. Several logic synthesis procedures, respective to various design styles and methodologies, can be used to design combinational parts of state machines, microprogrammed units, and data path logic. >

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Andisheh Sarabi

Papers

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams

Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks

A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays

Fast minimization of mixed-polarity AND/XOR canonical networks

Integration of logic synthesis and high-level synthesis into the DIADES design automation system