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Andreas Bernauer

Researcher at University of Tübingen

Publications -  19
Citations -  160

Andreas Bernauer is an academic researcher from University of Tübingen. The author has contributed to research in topics: Learning classifier system & System on a chip. The author has an hindex of 7, co-authored 19 publications receiving 154 citations.

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Design and Run-time Reliability at the Electronic System Level (IPSJ Transactions on System LSI Design Methodology Vol.3)

Abstract: The ongoing scaling of CMOS technology facilitates the design of systems with continuously increasing functionality but also raises the susceptibility of these systems to reliability issues. These can for example be caused by high power densities and temperatures. At the moment it is still possible to cope with the posed challenges in an affordable manner. But in the future, a combination of design and run-time measures will become necessary in order to guarantee that reliability guidelines are met. Because of complexity reasons, the Electronic System Level (ESL) is gaining importance as starting point of design. Design alternatives are evaluated at ESL with respect to several design objectives, lately also including reliability. In this paper, the most important phenomena threatening the reliability are introduced and the current status of related research work and tools is presented. After that, a high level design space exploration considering performance, energy and reliability trade-offs in multi-core systems is introduced. Finally, it is shown how reliability can be further improved during run-time by the application of a machine learning system.
Proceedings ArticleDOI

Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures

TL;DR: By applying activity migration the effects of continuous activity migration are investigated, which are able to reduce temporal and spatial variations of temperature by up to 87%.

Combining Software and Hardware LCS for Lightweight On-chip Learning.

TL;DR: This work combines the capabilities of a software-based LCS, the XCS, with a lightweight hardware implementation, the LCT, retaining the benefits of both, to realize a lightweight but very capable hardware implementation of a Learning Classifier System for on-chip learning.

Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoC

TL;DR: This work-in-progress paper surveys error detection techniques for transient, timing, permanent and logical errors in system-on-chip (SoC) design and discusses their applicability in the design of monitors for the Autonomic SoC architecture framework.