Fault-Tolerant Computer System Design by Dhiraj K. Pradhan 550 pp. $72 Prentice Hall Upper Saddle River, N.J. 1996 ISBN 0-13-057887-8

Fault-tolerant computer system design

Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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Multi-core Devices for Safety-critical Systems: A Survey

Fault-tolerant real-time tasks scheduling with dynamic fault handling

Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective

Despite the tremendous attention Unmanned Aerial Vehicles (UAVs) have received in recent years for applications in transportation, surveillance, agriculture, and search and rescue, as well as their possible enormous economic impact, UAVs are still banned from fully autonomous commercial flights. One of the main reasons for this is the safety of the flight. Traditionally, pilots control the aircraft when complex situations emerge that even advanced autopilots are not able to manage. Artificial Intelligence based methods and Adaptive Controllers have proven themselves to be efficient in scenarios with uncertainties; however, they also introduce another concern: nondeterminism. This research endeavors to find a solution on how such algorithms can be utilized with higher reliability. Our method is based on using an adaptive model to verify the performance of a control parameter — proposed by a nondeterministic adaptive controller or AI-based optimizer — before it is deployed on the physical platform. Furthermore, a backup mechanism is engaged to recover the drone in case of failure. A Neural Network is employed to model the aircraft, and a Genetic Algorithm is utilized to optimize the PID controller of a quadcopter. The initial experimental results from test flights indicate the feasibility of this method.

A reliable system design for nondeterministic adaptive controllers in small UAV autopilots

Modern avionic system development is undergoing a major transition, from federated systems to Integrated Modular Avionics (IMA) where several applications with mixed criticality will reside on the same platform. Moreover, there is a departure from today's single core computing, and we need to address the problem of how to guarantee determinism (in time and space) for application tasks running on multiple cores and interacting through shared memory. This paper summarizes the main challenges and briefly describes some active directions in research regarding temporal partitioning. It also outlines the forthcoming research that we will pursue for quantifying time bounds on memory access related interference, to ensure determinism and comply with certification requirements.

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Challenges in Future Avionic Systems on Multi-Core Platforms

Deployment of multi-core platforms in safety-critical applications requires reliable estimation of worst-case response time (WCRT) for critical processes. Determination of WCRT needs to accurately ...

https://drops.dagstuhl.de/opus/volltexte/2016/6905/pdf/OASIcs-WCET-2016-12.pdf/

Understanding Shared Memory Bank Access Interference in Multi-Core Avionics

The deployment of multi-core platforms in safety-critical avionic applications is hampered by the lack of means to ensure predictability when processes running on different cores can create interference effects, affecting worst-case execution time, due to shared memory accesses. One way to restrict these interferences is to allocate a budget for different processes prior to run-time and to monitor the adherence to this budget during run-time. While earlier works in adopting this approach seem promising, they focus on application level (user mode) accesses to shared memory and not the operating system accesses. In this paper we construct experiments for studying a multi-core platform running an ARINC 653 compliant operating system, and measure the impact of both application processes and operating system (supervisor mode) activities. In particular, as opposed to earlier works that considered networking applications, we select four avionic processes that exhibit different memory access patterns, namely, a navigation process, a matrix multiplication process, a math library process and an image processing one. The benchmarking on a set of avionic-relevant application processes shows that (a) the potential interference by the operating system cannot be neglected when allocating budgets that are to be monitored at run-time, and (b) the bounds for the allowed number of memory accesses should not always be based on the maximum measured count during profiling, which would lead to overly pessimistic budgets.

Andreas Löfwenmark

Papers

Challenges in Future Avionic Systems on Multi-Core Platforms

Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective

Understanding Shared Memory Bank Access Interference in Multi-Core Avionics

Experience report: Memory accesses for avionic applications and operating systems on a multi-core platform