A radio frequency power amplifier includes a feedback control system coupled to an input signal and a first feedback signal and configured to provide an output; a controlled supply configured to provide power that is controlled in accordance with a signal; and a radio frequency gain stage powered from the controlled supply, driven by the output from the feedback control system, and configured to provide an output signal at the radio frequency to a resonant load, where the first feedback signal corresponds to the output signal. Some embodiments include a sequencer in the feedback control system and others utilize an additional feedback loop to control the power provided by the controlled supply.

Radio frequency power amplifier and method using a controlled supply

This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All circuit blocks are realized using sub-1.0 V topologies, that feature only a single high-frequency transistor between the supply and ground, and which are scalable to future 45 nm, 32 nm, and 22 nm CMOS nodes. The transceiver is fabricated in a 65 nm CMOS process with a digital back-end. It includes a receiver with 14.7 dB gain and 5.6 dB noise figure, a 60 GHz LO distribution tree, a 69 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 6 Gb/s. With both the transmitter and the receiver turned on, the chip consumes 374 mW from 1.2 V which reduces to 232 mW for a 1.0 V supply. It occupies 1.28 times 0.81 mm2. The transceiver and its building blocks were characterized over temperature up to 85deg C and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on slow, typical, and fast process splits. The transceiver architecture and performance were validated in a 1-6 Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.

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A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

This paper presents a CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency when amplifying signals with high linearity requirements. The power amplifier comprises 64 parallel RF amplifiers that are driven by a constant envelope RF phase-modulated signal. The unit amplifiers are digitally activated by a 6-bit envelope code to construct a non-constant envelope RF output, thereby performing a digital-to-RF conversion. In order to suppress the spectral images resulting from the discrete-time to continuous-time conversion of the envelope, the use of oversampling and four-fold linear interpolation is explored. An experimental prototype of the polar amplifier has been integrated in a 0.18- mum CMOS technology, occupies a total die area of 1.8 mm2 , operates at a 1.6-GHz carrier frequency with a channel bandwidth of 20 MHz. For an OFDM signal, it achieves a power-added efficiency of 6.7% with an EVM of - 26.8 dB while delivering 13.6 dBm of linear output power and drawing 145 mA from a 1.7-V supply.

A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth

Summary form only given, as follows. Reference [1] is an expanded description of work presented at the 2007 IEEE International Solid-State Circuits Conference. At the time the manuscript was submitted to the IEEE Journal of Solid-State Circuits, July 2007, the authors were unaware of references [2] and [3] cited by the correspondents, and regret the omission of citations to this work.

Reply to Comments on “A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth”

An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Digital phase locked loop with dithering

A radio frequency digital-to-analog converter with a programmable current output. In exemplary aspects of the invention, improved apparatus and methods for providing (i) current mirror matching, (ii) enhanced current pulse rising edge performance, (ii) reduced base voltage swing, and (iv) compensated high voltage swing, are provided. The foregoing apparatus and methods can be applied to any RF signal application (wireless or otherwise), including for example wireless cellular handsets.

Radio frequency digital-to-analog converter

Improved radio frequency (RF) envelope tracking apparatus for use in wireless and wired systems. In one exemplary embodiment, a transmitter upconversion stage receives input digital I and Q values, the output of the upconversion stage being fed to both an envelope tracking circuit and a power amplifier (before or after optional filtering). The envelope tracking circuit controls the operation of a power modulator, which adjusts the power amplifier. The envelope tracking circuit is specifically configured to provide improved linearity and power efficiency. The envelope tracking apparatus and methods of the present invention may be applied to heterodyne/super-heterodyne architectures as well as others.

Andrew Tham

Papers

Radio frequency digital-to-analog converter

Radio frequency envelope apparatus and method

Improved radio frequency digital-to-analog converter