A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Delayed locked loop implementation in a synchronous dynamic random access memory

A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions

A charge pump circuit comprises a plurality of voltage doubler circuits connected together such that a first voltage output generated by a first portion of a kth one of the voltage doubler circuits is substantially equal to Vdd*2k and Vdd*2k-1) on odd and even phases, respectively, of a first clock signal, and a second voltage output generated by a second portion of the kth one of the voltage doubler circuits is substantially equal to Vdd*2k-1) and Vdd*2k on the odd and even phases, respectively, of the first clock signal. Each of the voltage doubler circuits is constructed such that when its first portion is providing a voltage of Vdd*2k and a current to a next stage, its second portion is recharging a capacitor in that portion to Vdd*2k-1), and when its second portion is providing a voltage of Vdd*22 and a current to the next stage, its first portion is recharging a capacitor in that portion to Vdd*2k-1). An output circuit is connected to a last one of the voltage doubler circuits to provide other circuitry with a substantially constant output voltage Vpp and output current Ipp, by providing such voltage and current from a first voltage output of the last voltage doubler circuit on odd phases of the first clock signal, and from a second voltage output of the last voltage doubler circuit on even phases of the first clock signal.

Charge pump circuit with exponetral multiplication

A level selectable FET voltage generation system is described. The system includes a single charge pump controlled by multiple feedback paths and a powerdown circuit. Each feedback path contains a capacitor divider network, a sense amplifier with a compensating voltage reference and a timer which periodically resets the capacitor divider network to insure sensing accuracy. The powerdown circuit and a selected feedback path provides a desired voltage level at the output of the charge pump.

On chip multiple voltage generation using a charge pump and plural feedback sense circuits

A charge pump circuit for generating an output voltage is described. The charge pump includes multiple output generation stages connected in series and a corresponding set of multiple gate stages connected in series, where the output stages have the same structure as the corresponding gate stages. The switches that the provide the output of each output generation stage are controlled by the corresponding gate stage. The number of output stages that are active in boosting the voltage self-adapts according to the output level being regulated, with the later stages changing from a boosting operation to a filtering function with not being used to active boost the output.

Self-Adaptive Multi-Stage Charge Pump

A charge pump for providing programming voltages to the word lines of a semiconductor memory array is disclosed. The charge pump, configured as a combination of enhancement and native MOS transistors, prevents DC current from flowing from the source of the programming voltage to ground through unselected word lines, and thereby permits the design of semiconductor programmable memory arrays having on-chip programming voltage generation, allowing for design of semiconductor programmable memory arrays which operate from a single voltage power supply.

Anil Gupta

Papers

Charge pump for providing programming voltage to the word lines in a semiconductor memory array