Systems and methods are provided for performing a quantum gate operation. The system includes a first physical qubit, and a second physical qubit operatively coupled to the first physical qubit via a coupling mechanism. The first physical qubit, the second physical qubit, and the coupling mechanism form a logical qubit. At least one control mechanism is configured to provide a control signal to one of the first physical qubit, the second physical qubit, and the coupling mechanism as to adjust a Hamiltonian of the logical qubit.

Quantum gates via multi-step adiabatic drag

An reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

Four-input Josephson gates

Systems and methods are provided for flux control of a qubit. A quantum system includes a microwave transmitter configured to provide a continuous microwave tone, and a qubit configured such that a portion of an energy spectrum of the qubit is responsive to an applied flux. The qubit also has an inductive element responsive to the continuous microwave tone to produce a Rabi oscillation within the qubit. A flux source is configured to apply a flux to the qubit.

Flux control of qubit under resonant excitation

The International Roadmap for Devices and Systems (IRDS) recently succeeded the International Technology Roadmap for Semiconductors (ITRS). The roadmap driver changed from scaling physical dimensions to application requirements and now includes a broader range of non-semiconductor technologies, such as superconductor electronics (SCE). We review current applications for SCE, ranging from development activities to small- scale commercial products. Computational accelerators within data centers and other future applications will require significant improvements in circuit density, complexity, functional capability, memory capacity, and data rates in and out of the cryogenic environment. As a first step, we propose to develop an application-driven roadmap for superconducting digital computing that will include key decisions to be made by the superconductor electronics community.

Superconductor Electronics and the International Roadmap for Devices and Systems

A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.

Josephson polarity and logical inverter gates

A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.

Phase-mode based superconducting logic

Superconducting circuits based devices and methods, including reciprocal quantum logic (RQL) based devices and methods are provided. In one example, a device comprising an output terminal, a first input terminal for receiving a first set of pulses, and a second input terminal for receiving a second set of pulses is provided. The first section may be configured to pass a single pulse received during a single clock cycle at any of the first input terminal or the second input terminal, but to not pass two or more positive pulses received during a single clock cycle at the first input terminal and the second input terminal. The second section, coupled to the first section, may be configured to, in response to the single pulse, generate a negative pulse after a predetermined fraction of a single clock cycle after providing a positive pulse at the output terminal.

Anna Y. Herr

Papers

Phase-mode based superconducting logic

Superconducting circuits based devices and methods