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Anthony B. Suppelsa
Researcher at Motorola
Publications - 39
Citations - 1652
Anthony B. Suppelsa is an academic researcher from Motorola. The author has contributed to research in topics: Substrate (printing) & Layer (electronics). The author has an hindex of 19, co-authored 39 publications receiving 1652 citations.
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Patent
Thermally conductive integrated circuit package with radio frequency shielding
TL;DR: In this article, a thermally and electrically conductive plastic material (20) containing metal particles is transfer molded to encapsulate the semiconductor device, the underfill adhesive, and a portion of the first side of the leadless circuit carrying substrate, forming a cover.
Patent
Method of forming a three-dimensional printed circuit assembly
TL;DR: In this article, a three-dimensional printed circuit assembly is formed by first making a substrate (20), a substrate is first formed from a photoactive polymer (14) that is capable of altering its physical state when exposed to a radiant beam (30). At this point, the substrate is only partially cured.
Patent
Method of making high density solder bumps and a substrate socket for high density solder bumps
TL;DR: In this article, a method of forming solder bumps includes the steps of applying a thick layer of solder resist (22) to a substrate (20), selectively removing to provide wells (23) at solder pads (21) on the substrate.
Patent
Ultra thin radio housing with integral antenna
Glenn F. Urbish,Quirino Balzano,Dale W. Dorinski,Martin J. Mckinley,Leng H. Ooi,John A. Stoutland,Anthony B. Suppelsa +6 more
TL;DR: In this paper, the authors describe a printed circuit loop antenna pattern that is vacuum-depositioned onto the thermoplastic base and/or cover, where the antenna pattern is disposed on both the cover and the base, and a portion of the antenna (e.g., 1002K) is also disposed on the hinge to join the main portions of antenna on the base and cover.
Patent
Pad grid array for receiving a solder bumped chip carrier
TL;DR: A pad grid array comprises an array of cavities formed in a circuit carrying substrate (10) that are metallized (18, 20, and 22) to provide electrical conductivity as discussed by the authors.