An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate). Since no wire bonds are required, the resulting package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.

Chip scale surface mount package for semiconductor device and process of fabricating the same

Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.

Surface mount package

A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance A MOSFET ( 70 ) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant ( 29 ), a plurality of outer leads ( 37 ), ( 38 ) protruding in parallel from the same lateral surface of the resin encapsulant ( 29 ) and a header ( 28 ) bonded to a back surface of the semiconductor pellet and having a header protruding portion ( 28 c) protruding from a lateral surface of the resin encapsulant ( 29 ) opposite to the lateral surface from which the outer leads protrude, wherein the header ( 28 ) has an exposed surface ( 28 b) exposed from the resin encapsulant ( 29 ); the outer leads ( 37 ), ( 38 ) are bent; and the exposed of the outer leads ( 37 ), ( 38 ) are provided at substantially the same height

Semiconductor device and a method of manufacturing the same

A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).

Semiconductor die package using leadframe and clip and method of manufacturing

A semiconductor device (60) is disclosed, comprising: a semiconductor die (62) including top and bottom surfaces, the semiconductor die (62) further comprising a source contact area (64), a gate contact area (66), and a drain contact area, wherein the contact areas (64, 66) are arranged on a selected one of the top and bottom surfaces; a drain lead (72) comprising a top surface, a bottom surface (72c), and a coupling portion (72a) coupled to the drain contact area of the semiconductor die (62); and an encapsulant (74) enclosing a portion of the semiconductor die (62) and a portion of the drain lead (72) such that the bottom surface (72c) of the drain lead (72) remains exposed.

IC chip package with directly connected leads

A semiconductor device (100) comprising: a semiconductor die (102) including top and bottom surfaces, the semiconductor die (102) further comprising a source contact area and a gate contact area, wherein the contact areas are arranged on opposite portions of a selected one of the top and bottom surfaces; a source lead (103) comprising a first portion coupled to the source contact area, and a second portion extending from the first portion and protruding from a first side of the semiconductor die (102); a gate lead (103) comprising a first portion coupled to the gate contact area, and a second portion extending from the first portion and protruding from a second side opposite the first side of the semiconductor die (102); and an encapsulant (104) enclosing at least a portion of the semiconductor die (102) and at least a portion of the source lead (103) and the gate lead (103).

Power MOSFET package with directly connected leads

PROBLEM TO BE SOLVED: To provide a semiconductor device structure which reduces the ON- resistance and superior radiation characteristics. SOLUTION: A semiconductor device has a semiconductor chip 12 having a contact region on an upper and lower surface, first and second lead assemblies are each made from a half-hard sheet of a conductive material and have lead assembly contacts each separately mounted on one contact region of the semiconductor chip 12, the first and second lead assemblies are connected to the respective lead assembly contacts and have at least one lead extending therefrom, a seal body seals the semiconductor chip 12 and lead assembly contacts of the first and second lead assemblies, and since the lead assemblies are directly coupled with chip, the electric and thermal resistances concerning the package become lower.

Anthony C. Tsui

Papers

IC chip package with directly connected leads

Power MOSFET package with directly connected leads

Ic chip package with directly fixed leads