The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

The invention provides a method and system for receiving incoming information from multiple information sources, both interactive and passive, and for engagingly presenting that information to a recipient on a presentation interface. The system includes a “background” element, which interacts with interactive information sources and receives from passive information sources, and determines whether information from those sources is likely to be interesting to the recipient, possibly using one information source to determine priority for another. The system also includes a “foreground” element, which presents information to the recipient when active, but not when inactive. The background is operative even when the foreground element is inactive, and when the background detects new information of interest to the recipient (for example, exceeding a selected threshold of interest or satisfying a selected criterion for interest), it causes the foreground to become active and engage the recipient to select and view that new information. The threshold or criterion may be adaptively responsive to recipient preferences, whether explicitly expressed or implied, but may also be relatively fixed, such as a scheduled time of day.

Information retrieval system using an internet multiplexer to focus user selection

A disk storage subsystem includes both volatile and non-volatile portions of memory. In response to a write command from a host computer, the controller allocates a predetermined number of memory blocks in the non-volatile cache memory and allocates a corresponding number of blocks in the volatile memory. Host supplied write data is then stored in the allocated non-volatile memory blocks. The data may also be mirrored in additional non-volatile memory. Immediately thereafter the subsystem sends an acknowledge signal to the host. The subsystem then performs a DMA operation to copy the write-data from the non-volatile memory blocks to the volatile memory blocks. The write-data is then stored on a disk drive at which point the non-volatile memory may be de-allocated. Subsequent reads of the given data may be read from the volatile memory, reducing disk access time. In the event of a power failure, data stored in the non-volatile memory but not yet written to disk is preserved. In the event of a disk controller failure, the non-volatile memory modules may be transferred to a functioning disk controller for recovery.

Disk controller with volatile and non-volatile cache memories

A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Video and graphics system with parallel processing of graphics windows

A video processing module designed for high performance using economical components. A programmable logic device (PLD) is configured to modify a data stream, in particular a video stream. The PLD can be connected to a memory resource. In addition, the PLD can be connected to a second PLD through an interruptable connection. The second PLD can be optimized for bus interface communication and connected to an external system, typically a host computer. The second PLD can take commands from the host to prepare a processing configuration for the first PLD and can connect when needed to download a configuration to the first PLD through the interruptable connection. An array of these modules can be connected in a systolic array to provide powerful, pipelined video processing.

Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation

An arrangement which includes apparatus for signifying the source of data to be displayed, apparatus for generating lines of data to fit between the lines of interlaced data to be presented on a non-interlaced output display device, and apparatus for generating lines of data to be presented on an interlaced display from a larger number of lines representing non-interlaced data.

Apparatus for providing output filtering from a frame buffer storing both video and graphics signals

A circuit for providing control signals of selectable lengths capable of being driven off of either the rising or falling edge of a clock pulse, the circuit comprising apparatus for providing signals indicating a mode of operation for access to a matrix of memory elements, apparatus responsive to the signals provided by the apparatus for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to commence and the edge of the clock signal at which such signal is to commence, and apparatus responsive to the signals provided by the apparatus for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to terminate and the edge of the clock signal at which such signal is to terminate.

Programmable memory state machine for providing variable clocking to a multimode memory

An arrangement for storing information to be displayed in a plurality of different pixel formats on a bitmapped output display including apparatus for selecting first positions for storage of information in a first pixel format, apparatus for selecting second positions for storage of information in a second pixel format, apparatus for selecting information from first positions of storage for display in the first pixel format, and apparatus for selecting information from second positions of storage for display in the second pixel format.

Apparatus for storing information in and deriving information from a frame buffer

A cache management system for a computer system having a central processing unit, a main memory, and cache memory including a memory management unit for transferring page size blocks of information, apparatus for reading information from main memory, apparatus for writing information to the cache memory, and apparatus for overlapping the write of information to the cache memory to occur during the read of information from the main memory.

Apparatus and method for improved caching in a computer system

Apparatus for converting representations of color pixels in a twenty-four bit color format to representations in a fifteen bit color format including an individual circuit for data representing each component of a color, each of the individual circuits including apparatus for selectively incrementing the value the five highest order bits of a value representing a component of a color, apparatus responsive to a value of the lowest order bits of a value representing a component for providing a signal to cause the apparatus for selectively incrementing the five highest order bits, and apparatus for selectively enabling the apparatus responsive to a value of the lowest order bits depending on a desired pattern of pixels.

Anthony D. Masterson

Papers

Apparatus for providing output filtering from a frame buffer storing both video and graphics signals

Programmable memory state machine for providing variable clocking to a multimode memory

Apparatus for storing information in and deriving information from a frame buffer

Apparatus and method for improved caching in a computer system

Apparatus for converting twenty-four bit color to fifteen bit color in a computer output display system