A integrated phone-based home gateway system is disclosed. The integrated phone-based home gateway system includes a broadband communication device, such as digital subscriber line (“DSL”) device, an analog modem, a wireless interface, integrated into a screen-phone for providing broadband communication service to home users. Multiple home users are able to access the Internet and the content services for conducting e-commerce, receiving content news, entertaining on-demand, making audio or video communications, and telecommuting or working at home. This screen-phone based, modular, plug-n-play home gateway interface allows in-home as well as to-home networking, provides automatic data and broadband initialization, configuration and service provisioning, routing and bridging functionality and allows resource sharing among home devices via the existing phone wire, wireless, coaxial or optical cable connections.

Broadband communications access device

A serial intelligent cell (SIC) and a connection topology for local area networks using Electrically-conducting media. A local area network can be configured from a plurality of SIC's interconnected so that all communications between two adjacent SIC's is both point-to-point and bidirectional. Each SIC can be connected to one or more other SIC's to allow redundant communication paths. Communications in different areas of a SIC network are independent of one another, so that, unlike current bus topology and star topology, there is no fundamental limit on the size or extent of a SIC network. Each SIC can optionally be connected to one or more data terminals, computers, telephones, sensors, actuators, etc., to facilitate interconnectivity among such devices. Networks according to the present invention can be configured for a variety of applications, including a local telephone system, remote computer bus extender, multiplexers, PABX/PBX functionality, security systems, and local broadcasting services. The network can use dedicated wiring, as well as existing wiring as the in-house telephone or electrical wiring.

Local area network of serial intelligent cells

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

System and method for communicating with an integrated circuit

The present invention relates to various methods of collecting and using data from RFID tags associated with items of interest. In one embodiment, the permissible error tolerance associated with the location of an RFID-tagged item may be altered, either manually or automatically. In another embodiment, RFID-tagged items may be associated with certain categories of items, based either on default or user-specified categories.

Rfid data collection and use

A resynchronization circuit for processing a stream of data values read from a memory system, and a method of operating the same. The resynchronization circuit includes a first in, first out (FIFO) memory device, a phase locked loop circuit and a latency control circuit. The FIFO memory device receives a stream of data values and a first clock signal from the memory system. The data values are sequentially read into the FIFO memory device in response to the first clock signal. The phase locked loop circuit receives a second clock signal, and in response generates an output clock signal which leads in phase the second clock signal. The output clock signal is provided to the FIFO memory device to cause the data values to be sequentially read from the FIFO memory device. As a result, a stream of data values is generated which is synchronized with the second clock signal. The latency control circuit, which is coupled to the FIFO memory device, enables the data values to be read from the FIFO memory device after a selectable delay period which follows the initiation of the read operation from the memory system.

Resynchronization circuit for a memory system and method of operating same

An integrated line-card terminates an asymmetric digital-subscriber line (ADSL) copper-pair at a single point in a central office. The line card contains analog line circuitry such as a ring generator, off-hook detector, D.C. current feed, and a single analog-digital (A/D) converter. The phone line carries a composite signal of both the high-frequency ADSL data and the low-frequency voice or plain-old-telephone-service (POTS) signal. Instead of using an analog frequency-splitter with bulky, expensive inductor coils, a digital splitter is used. A digital-signal processor (DSP) can be used to perform the digital splitting of ADSL and POTS. The waveforms from the analog phone line are first converted to digital values by the A/D converter, and then a digital splitter separates the low-frequency POTS from the high-frequency ADSL. The ADSL data is formatted by the DSP for a data pathway to the Internet, while the POTS data is converted by the DSP to A-Law or C-Law for transmission over the telephone network's PCM highway. The DSP can perform all decoding, encoding, compression, and formatting needed by both ADSL and POTS. The quality of the phone line is improved by having a single termination point at the central office, rather than separate termination points for POTS and ADSL data from the phone line.

ADSL integrated line card with digital splitter and POTS CODEC without bulky analog splitter

A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which descriptors of data buffers are stored in a circular descriptor queue. The descriptors of those data buffers that are currently available for use in a DMA transfer are maintained in contiguous locations in the descriptor queue. The location of the first available descriptor and the number of currently available descriptors in the descriptor queue are provided to a network controller. Based on this information, the network controller then obtains a set of available descriptors and fills the corresponding buffers with data as it arrives on the different channels. When the use of a data buffer in a DMA transfer is complete, the descriptor for this buffer is made available again in the descriptor queue by re-filling this descriptor immediately following the available descriptors. No matter in which order the individual channels of the multi-channel system use and return the data buffers, the available descriptors are maintained in contiguous locations in the descriptor queue, increasing the efficiency of the system since searching through the descriptor queue for available descriptors is not required.

System for managing direct memory access transfer in a multi-channel system using circular descriptor queue, descriptor FIFO, and receive status queue

A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which a sequence of data frames are received at a controller that controls a DMA transfer. The data frames are placed in data buffers in a memory by the controller. Multiple data frames are stored by the controller in at least one of the data buffers. The storing of multiple data frames in a single buffer provides efficient utilization of memory space as large size buffers are used to hold more than a single data frame, and also reduces the management overhead involved in placing the data frames in the data buffers.

Method and apparatus for placing multiple frames of data in a buffer in a direct memory access transfer

This invention provides a flexible, general-purpose, engine-based architecture for a multi-channel data communications controller. It can be customized to handle a wide range of protocols and other host system requirements with minimal reliance on the host's processing power. The always present time-critical tasks of transmitting and receiving serial data, as well as transmitting and receiving characters to/from the host, are handled quickly and efficiently by utilizing dedicated interface processors. This leaves the general purpose main engine less burdened with these time cricital tasks, enabling it to perform the relatively more complex (though less time critical) tasks of assembling and disassembling characters, as well as maintaining RAM-based data FIFOs and performing error-checking and other protocol-related tasks. Custon protocols can be implemented merely by re-microcoding the machine, without requiring modifications to the basic architecture of the chip, substantially reducing design time. The flexibility of this general purpose architecture enables controllers to be more customized to a particular user's requirements, resulting not only in faster performance by the controller itself, but also in far less reliance on the host's processing power. What could previously only be done by the host in software can now be done by the controller itself much more quickly.

Multi-channel data communications controller

A bi-level framing structure for DSL phone systems uses 4 KHz physical frames and mux data frames. The mux data frames each start with a sync byte and contain user payload bytes. A group of mux data frames are appended with forward-error-correction FEC bytes to make a codeword. The codeword is then partitioned into physical 4-KHz frames. The physical frames are transformed by an inverse fast-Fourier transform (IFFT) outputting symbols at 4 KHz for transmission. For high line rates, each codeword has S mux data frames and S physical frames. There are also at least S FEC bytes if error correction is enabled. However, for lower line rates, there are S physical frames but only S/M mux data frames in each codeword. The efficiency factor M is 1 for high line rates, but 4 for lower line rates. Reducing the number of mux data frames reduces the number of sync bytes in a codeword, decreasing overhead. The FEC bytes are spread among more physical frames, reducing error-correction overhead. The symbol rate and the rate of physical frames remains at 4 KHz, even at the lower line rate. The smaller number of bytes per symbol at the lower line rates is compensated for by reducing the number of mux data frames per 4 KHz frame, allowing larger, more efficient mux data frames and error correction to be used. Thus bandwidth efficiency is increased for lower line rates.

Anthony J. P. O'Toole

Papers

ADSL integrated line card with digital splitter and POTS CODEC without bulky analog splitter

System for managing direct memory access transfer in a multi-channel system using circular descriptor queue, descriptor FIFO, and receive status queue

Method and apparatus for placing multiple frames of data in a buffer in a direct memory access transfer

Multi-channel data communications controller

Bi-level framing structure for improved efficiency DSL over noisy lines