Image processing method and apparatus wherein candidate points are first selected in a log-polar image domain. The points may be selected by edge detection, thresholding, or any method suitable for identifying image points which are likely to lie on some feature of interest. For every candidate point there is drawn, also in the log-polar domain, a mirror image of a curve that represents the log-polar image of a straight line. There is accumulated a log-polar domain histogram of "hits" from the drawing process. Finally, a peak bin is selected. The position of the peak bin corresponds to the position of the recognized line.

Method and means for recognizing patterns represented in logarithmic polar coordinates

An information extraction device including a coordinate transformation unit for transforming the coordinate values of points on a plane in question to the coordinate values of the points on a spherical surface corresponding to the points on the plane, and a mapping unit for mapping the points on the spherical surface to great circles. This information extraction device is applicable to the detection of the three-dimensional direction of a single line or a single plane existing in space.

Information extraction by mapping

Systems and methods for converting a baseband OFDM signal to an IF signal while minimizing lengthening of the impulse response duration experienced by the OFDM signal. A conversion technique according to the present invention provides sufficient filtering to limit the effects of spurious frequency domain components caused by transitions between successive OFDM bursts. In one embodiment, the filtering is provided by a combination of a finite impulse response (FIR) filter having non-linear phase characteristics and a cyclic convolution filter. Conversion from the frequency domain into the time domain, upsampling, and cyclic filtering may be combined into one operation.

Optimal filtering and upconversion in OFDM systems

A monolithic convolver circuit making extensive use of "pipelined" architecture to ensure high speed by concurrency of processing, and having a repetitive stage to facilitate chip layout and manufacture. The circuit includes a multiplier and an adder in each stage. The adders produce a sequence of summation terms concurrently and include shift registers to move and accumulate the results of convolution. The adders produce only partial sums at each stage, to increase processing speed. Full computation of carries is deferred until the very end, and performed in a separate conditional sum adder.

Monolithic discrete-time digital convolution circuit

An FIR digital filter device of the symmetrical coefficient type or the antisymmetrical coefficient type or which processes digital data signals such as digital audio signals. In the FIR digital filter device, a digital input data is transferred in the forward direction through a plurality of digital signal processors (F, B) connected in cascade and is then transferred in the reverse direction to form M pieces of delayed digital data. The digital signal processor in each stage effects the algebraic addition of said delayed digital data and the digital input data through a first operation unit (46), effects the multiplication result through a multiplier (47), adds up the multiplied result through a second operation unit (37), and transfers the obtained data as carry-over data to the next stage.

Finite impulse response (fir) filter using a plurality of cascaded digital signal processors (dsps)

A circuit for transforming to polar coordinate form first and second binary number electrical signals representative of rectangular coordinates or quadrature components for a vector or phasor. The circuit utilizes a programmable memory in which values corresponding to the sine and cosine functions are stored. In the preferred form, the circuit utilizes binary number electrical signals of 10 bits. The most significant bit of the polar coordinate angle is found directly from the binary number representing one of the quadrature components, whereas the next two most significant bits of the angle are found using logic circuitry in association with the binary number signals representing the quadrature components. The remaining bits of the angle are found by use of a successive approximation technique in conjunction with the values stored in the memory. Once the angle is determined, the amplitude of the vector or phasor is determined by the use of the function P = Im(sinθ) + Re(cosθ) where Im and Re are the quadrature components. The coordinate transforming circuit is particularly useful in digital transmission and receiving systems in connection with modulation of transmitted signals and demodulation of received signals.

Circuit for transforming rectangular coordinates to polar coordinates

A digital linear phase shift convolutional filter for filtering a series of binary number electrical signals each of which represents the magnitude of a sample of an analog electrical signal sampled at a predetermined rate. The convolutional filter utilizes a bidirectional shift register and a preferably unidirectional shift register. Each of the registers has a plurality of stages. The bidirectional shift register receives the serially presented binary number electrical signals representative of the sample magnitudes, and these samples are sequentially transferred from the output stage of the bidirectional shift register to the input stage of the unidirectional shift register. During the interval between receipt in the bidirectional shift register of binary number electrical signals representative of the sample amplitudes, the binary number electrical signals stored in the bidirectional shift register are shifted in a recirculating fashion, as are the binary number electrical signals stored in the unidirectional shift register. The binary number electrical signals appearing in particular stages of each of the registers are combined arithmetically to produce a resultant binary number electrical signal with each shift in the recirculating shift registers. These resultant signals are multiplied by constant values representing filter weights, and the products are summed to produce an output binary number electrical signal. One such output signal is produced for each new sample that enters the bidirectional shift register.

Digital convolutional filter

A digital click removal and squelch control circuit for a digital FM receiver. The digital receiver generates a series of binary number electrical signals each of which is representative of the instantaneous phase angle of a received frequency-modulated electrical signal or signal derived therefrom. The phase angle signals are differentiated to produce binary number electrical signals that represent the rate of change of phase angle, or, the instantaneous frequency of the received signal. During a given time interval, the phase change caused by the modulation of the received signal must be within a range determined by the bandwidth of the received frequency-modulated signal. Phase changes outside of this range represent electrical noise or clicks and are removed by the click removal circuit of the invention. If a predetermined number of clicks occur during a predetermined time interval, the squelch control circuit of the invention provides a squelch control signal which may be used to disable the output of the FM receiver. When the click rate decreases, the output of the FM receiver is restored.

Anthony Mattei

Papers

Circuit for transforming rectangular coordinates to polar coordinates

Digital convolutional filter

Digital click removal and squelch control circuit for an FM receiver

Digitale knackgeraeuschunterdrueckungsund rauschsperrensteuerschaltung