The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

[서평]「Applied Cryptography」

Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.

https://www.eecs.ucf.edu/~jinyier/courses/EEE4932/Papers_Final/HARPOON%20-%20An%20Obfuscation-Based%20SoC%20Design%20Methodology%20for%20Hardware%20Protection.pdf

HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

As the electronic component supply chain grows more complex due to globalization, with parts coming from a diverse set of suppliers, counterfeit electronics have become a major challenge that calls for immediate solutions. Currently, there are a few standards and programs available that address the testing for such counterfeit parts. However, not enough research has yet addressed the detection and avoidance of all counterfeit partsVrecycled, remarked, overproduced, cloned, out-of-spec/defective, and forged documentationVcurrently infiltrating the electronic component supply chain. Even if they work initially, all these parts may have reduced lifetime and pose reliability risks. In this tutorial, we will provide a review of some of the existing counterfeit detection and avoidance methods. We will also discuss the challenges ahead for im- plementing these methods, as well as the development of new detection and avoidance mechanisms.

/pdf/counterfeit-integrated-circuits-a-rising-threat-in-the-1cfbkrfgxn.pdf

Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain

From the Publisher:
Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks.
An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries.
Switching Theory for Logic Synthesis is based on the author's lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies.
Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.

/pdf/switching-theory-for-logic-synthesis-kmi9ehlc6k.pdf

Switching Theory for Logic Synthesis

Multivalued logic has always attracted the attention of digital system and logic designers. However, the high-performance and low-power CMOS process, which has been developed over the last two decades, has traditionally assisted successful circuit implementation of binary logic. Consequently, in spite of its large potential multivalued logic design is seldom a circuit designer's choice. This paper presents a novel method of multiple-valued logic design using carbon-nanotube field-effect transistors (CNFETs). The geometry-dependent threshold voltage of CNFETs has been effectively used to design a ternary logic family. We have developed a SPICE-compatible model of ballistic CNFETs that can account for varying geometries and operating conditions. SPICE simulations have been performed on the proposed logic gates, and the transfer characteristics as well as transient behavior have been extensively studied. Finally, a comparison in terms of power and performance of the ternary logic family vis-a/spl grave/-vis traditional complementary field-effect transistor binary logic family has been presented.

Carbon-nanotube-based voltage-mode multiple-valued logic design

In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

Currently, several design barriers inhibit the implementation of high-precision digital signal processing (DSP) systems with field programmable logic (FPL) devices A new demonstration of the synergy between the residue number system (RNS) and FPL technology is presented in this paper The quantifiable benefits of this approach are studied in the context of a high-end communications digital receiver A new RNS-based direct digital synthesizer (DDS) that does not need a scaler circuit is introduced The programmable decimation FIR filter is based on the arithmetic benefits associated with Galois fields and supports tuning the IF frequency as well as its bandwidth Results show the proposed methodology requires fewer resources than classical designs, while throughput advantage is about 65%

http://senna.ugr.es/papers/lncs02_RNSrcv.pdf

Fast RNS FPL-based Communications Receiver Design and Implementation

Residue number system (RNS) is explored for implementation of fast digital signal processors with the design of an RNS-based SIMD RISC processor. Simulations conducted on programmable logic show a sustained advantage over commercial chips for a representative set of applications, while prospective results on VLSI technology are also promising.

RNS-enabled digital signal processor design

Previous scaling schemes have used iterative algorithms, which lead to computation time and memory requirements that increase with the number of moduli. This paper presents a two look-up cycle scaling scheme which allows a diminution of the required memory when nonlarge sets of moduli are considered. This scheme can be combined with previous algorithms for larger sets of moduli.

A look-up scheme for scaling in the RNS

The design of high performance, high precision, real-time digital signal processing (DSP) systems, such as those associated with wavelet signal processing, is a challenging problem. This paper reports on the innovative use of the residue number system (RNS) for implementing high-end wavelet filter banks. The disclosed system uses an enhanced index-transformation defined over Galois fields to efficiently support different wavelet filter instantiations without adding any extra cost or additional look-up tables (LUT). A selection of a small wordwidth modulus set are the keys for attaining low-complexity and high-throughput. An exhaustive comparison against existing two's complement (2C) designs for different custom IC technologies was carried out. Results reveal a performance improvement of up to 100% for high-precision RNS-based systems. These structures demonstrated to be well suited for field programmable logic (FPL) assimilation as well as for CBIC (cell-based integrated circuit) technologies.

Antonio Lloris

Papers

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

Fast RNS FPL-based Communications Receiver Design and Implementation

RNS-enabled digital signal processor design

A look-up scheme for scaling in the RNS

Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies