Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Reverse side engineered iii-nitride devices

A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

Enhancement Mode III-N HEMTs

Enhancement mode III-nitride devices are described The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate Both gallium face and nitride face devices formed as enhancement mode devices

Enhancement mode gallium nitride power devices

Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Semiconductor heterostructure diodes

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Semiconductor devices with field plates

When a field effect transistor is used to control the current through an inductive load, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate. This current represents a power loss and a source of heat. This invention supplies a second lateral transistor which conducts this current back to the power supply.

High voltage integrated flyback circuit in 2 μm CMOS

In the UNIX Operating System, modifying the kernel routine Physio, to enable a single system call to set up a number of concurrent direct memory access (DMA) channels between memory and the data buffers of a device. Many character device drivers use the UNIX Physio facility for I/O. The traditional implementation of Physio handles I/O in a serial manner by performing gather-write or scatter-read operations. This invention is an enhancement to Physio to support parallel I/O operations.

Aram Nahidipour

Papers

High voltage integrated flyback circuit in 2 μm CMOS

Method of using the UNIX physio to allow data to be transferred on a plurality of channels concurrently