Disclosed are methods and systems related to a Personal Assistance Safety System. In one aspect, disclosed are methods and systems for vehicle communications comprising an antenna selecting unit configured to select an antenna according to an antenna selection strategy and a first antenna switch coupled to the antenna selecting unit configured to direct communications through the selected antenna.

Personal Assistance Safety Systems and Methods

A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure data store; and restoring of said processed secure data using said secure key; wherein said secure key is securely stored such that it is not accessible to other processes operating in said non-secure mode.

Protecting the security of secure data sent from a central processor for processing by a further processing device

In one embodiment of the present invention, a secure cryptographic circuit arrangement is provided. The secure cryptographic circuit includes a cryptographic processing block, a spreading sequence generator, and a delay control circuit. The cryptographic processing block has a plurality of signal paths. One or more of the plurality of signal paths includes respective adjustable delay circuits. The spreading sequence generator is configured to output a sequence of pseudo-random numbers. The delay control circuit has an input coupled to an output of the spreading sequence number generator and one or more outputs coupled to respective delay adjustment inputs of the adjustable delay circuits. The delay control circuit is configured to adjust the adjustable delay circuits based on the pseudo-random numbers.

Method and integrated circuit for secure encryption and decryption

Disclosed are a method and device for generating a digital signature. The method comprises: a device generating a digital signature parameter r that meets an effective determining condition; generating a digital signature parameter s according to the following formula s = ((1 + d A ) -1 ·( r + k ) -r ) mod n, by using a private key d A , a random number k, r, and an elliptic curve parameter n , a value range of k being [1, n -1]; determining if the generated s is 0; if s is 0, regenerating r that meets the effective determining condition, and regenerating s by using d A , the regenerated k with the value range of [1, n -1] and the regenerated r and n , until s is not 0; converting data types of r and s that is not 0 into byte strings, to obtain a digital signature ( r , s ). According to the technical solutions provided by embodiments of this application, a digital signature parameter s is obtained by using a simplified calculation formula, and the number of times that big integers are calculated can be reduced, so that the calculation efficiency of generating a digital signature based on an SM2 digital signature generation algorithm is improved.

Method and device for generating digital signature

A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Random timeslot controller for enabling built-in self test module

An authentication system and a method for signing data are disclosed. The system uses a hardware software partitioned approach. In its implementation the system of the invention compares favourably with performance and other parameters with a complete hardware or full software implementation. Particularly, advantageously there is a reduced gate count. Also as disclosed in the invention the system makes it difficult for hackers to attack the system using simple power analysis.

Aravamuthan Sarangarajan

Papers

Authentication system executing an elliptic curve digital signature cryptographic process

An authentication system executing an elliptic curve digital signature cryptographic process