Efficient switched network multicasting techniques are provided. Incoming multicast packets are processed by a central forwarding engine (CFE) in a network switch to generate forwarding indices used to make forwarding decisions for the packets based upon whether the packets are special multicast control packets or data packets. Forwarding of the special multicast control packets is determined by the switch's network management processor (NMP), while data packets are forwarded based upon conventional bridge forwarding techniques.

Efficient network multicast switching apparatus and methods

A high aperture active matrix liquid crystal display (AMLCD) includes pixel electrodes in respective pixels which overlap adjacent address lines. The color filters are formed on the active substrate in a manner such that the filters also overlap the address lines and function as an insulating layer between the pixel electrodes and address lines in the areas of overlap. Accordingly, line-pixel capacitances are reduced and the resulting AMLCD is easier to manufacture. The total number of process step in manufacturing is reduced, and plate-to-plate (active to passive plate) alignment is much easier and less important.

High aperture LCD with insulating color filters overlapping bus lines on active substrate

The present invention is directed to a method and system for storing and managing objects, such as binary large objects (blobs) in a digital library system which includes a plurality of clients, an object server for storing an object, a cache server for storing an copy of the object, and a centralized server for storing information identifying the object as being stored in the object server and associating one or more of the clients with the cache server, in which one of the clients, as a requesting client, requests retrieval of an object, a copy of the requested object is sent from the cache server to the requesting client if the object is stored in said cache server, and a copy of said object is sent from the object server to said requesting client if the object is not stored in the cache server; and a copy of the requested object is sent from the object server to the cache server after the object server sends the object to the client, in which the object sent to the client is made available to the client regardless of whether sending of the copy of the object to the cache server is completed.

Distributed storage management system having a cache server and method therefor

A physical interconnection architecture for making connections between a plurality of first printed-circuit boards and a plurality of second printed-circuit boards includes a midplane printed-circuit board having a plurality of first connectors oriented in a first direction on one side of the midplane for making connections to the plurality of first printed-circuit boards. The midplane printed-circuit board also has a plurality of second connectors oriented in a second direction orthogonal to the plurality of first connectors on the other side of the midplane. The connectors are positioned such that connection pins on the plurality of first connectors and plurality of second connectors in regions of intersection are double-ended pins common to both. The remaining connection pins of the plurality of first connectors are single-ended connection pins which are connected to the single-ended connection pins of the plurality of second connectors via conductive traces on the midplane printed-circuit board.

Switching midplane and interconnection sytem for interconnecting large numbers of signals

A large flat IP network is created in a switched layer-2 network by adjusting the subnet masks of hosts such that these hosts can communicate directly with other hosts without the use of an intermediate router. The layer-2 switches are configured with user-selected IP subnets and monitor and analyze multicast packets to learn the mapping between IP subnets and switch ports. The layer-2 switches selectively forward the mulitcast packets based on the learned mappings between IP subnets and ports. After the destination host responds to the forwarded multicast, a direct connection is established between the source and destination hosts using the media access control addresses of both hosts.

Method and system for subnetting in a switched IP network

A physical cache unit (100) is used within a computer (20). The computer (20) further includes a main memory (99) a memory control unit (22), inputs/output processors (54, 68) and a central processor (156). The central processor includes an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144) and vector processing units (148, 150). The physical cache unit (100) stores operands in a data cache (180), the operands for delivery to and receipt from the control processor (156). Addresses for requested operands are received from the central processor (156) and are examined concurrently during one clock cycle in tag stores (190 and 192). The tag stores (190 and 192) produce tags which are compared in comparators (198 and 200) to the tag of physical addresses received from the central processor (156). If a comparison is made, a hit, both of the requested operands are read, during one clock period, from the data cache (180) and transmitted to the central processor (156). If the requested operands are not in the data cache (180) they are fetched from the main memory (99). The operands requested from the main memory (99) within a block are placed in a buffer (188) and/or transmitted directly through a bypass bus (179) to the central processor (156). Concurrently, the block of operands fetched from main memory (99) may be stored in the data cache (180) for subsequent delivery to the central processor (156) upon request. Further, a block of operands from the central processor (156) can be transmitted directly to the memory control unit 22 and bypass the data cache (180).

Cache store bypass for computer

Physical cache unit for computer

An auxiliary connector circuit is used within an electronic system (10) which comprises a plurality of removable circuit cards (14, 16, 18, 20, 22, 24, 26) which are mounted within a cabinet (12). Before the circuit card (16) is removed from the cabinet (12), a power cable (44) is connected by means of engaging a plug (46) to a socket (34). When this occurs a DATA OUT ENABLE signal at a line (65) drives three-state devices (86, 88, 90, 92, 94, 96, 98 and 100) to a high impedance state to isolate a memory array (78) from a data bus (102). This high impedance prevents any transients from being transmitted through the data bus (102) when the card (16) is removed from the cabinet (12). After the card (16) is removed from the cabinet (12), the power cable (44) can be disconnected from the card (16) or the card (16) can be tested to evaluate the components mounted on the card (16).

Auxiliary power connector and communication channel control circuit

A read/modify/write circuit (10) for a computer is used in conjunction with a main memory (12) in which block operations are executed using a plurality of data units. The circuit (10) includes a first register connected to receive a data block from the main memory (12), a second register connected to receive data units from a requestor, such as a processor (18) and a third register in which a resulting data block is produced which comprises the data units to be written into the main memory (12) and the remaining data units which were previously in the block read from memory (12). Multiplex circuits (70, 72, 74, 76, 78, 80, 82 and 84) are commanded by a decoder (136) in response to the processor (18) to selectively route sections of registers (26 and 28) into a register (106). The resulting data block is then transferred through the memory bus (14) for writing into the main memory (12). The outputs of the multiplexors (70-84) can be driven by the decoder (136) to a predetermined logic state so that a selected data block can be written into the main memory (12) for test and evaluation purposes.

Read/modify/write circuit for computer memory operation

A memory array unit (20) is used within a main memory (26) of a computer system (10). The memory (26) comprises a plurality of memory array units (20, 22, 24) and each of the memory array units (20, 22, 24) has an allocated address range of 0 to 16 megabytes. However, the memory array unit (20) has a capacity of only four megabytes. The usable address range is 0 to 2 megabytes and 8 to 10 megabytes. The remainder of the address range is a null. Upon development of an increased memory array unit (20) having a greater capacity, such as 16 megabytes, the new memory array unit (20) is directly substituted for the previous low capacity memory array unit. The new memory array unit (20) has a fully implemented address range from 0 to 16 megabytes. The low and high capacity memory array units can be intermixed or the low capacity units can be entirely replaced by the high capacity units without the need for modifying any of the computer system (10) or for modifying the system software.

Arthur T. Kimmel

Papers

Cache store bypass for computer

Physical cache unit for computer

Auxiliary power connector and communication channel control circuit

Read/modify/write circuit for computer memory operation

Intermixing of different capacity memory array units in a computer