Introduction to linear and nonlinear programming

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed.

Clock distribution networks in synchronous digital integrated circuits

We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use additional forces to reduce cell overlaps and to consider the placement area. Compared to existing approaches, the main advantage is that the algorithm provides increased flexibility and enables a variety of demanding applications. Our algorithm is capable of addressing the problems of global placement, floorplanning, timing minimization and interaction to logic synthesis. Among the considered objective functions are area, timing, congestion and heat distribution. The iterative nature of the algorithm assures that timing requirements are precisely met. While showing similar CPU time requirements it outperforms Gordian by an average of 6 percent and TimberWolf by an average of 8 percent in wire length and yields significantly better timing results.

Generic global placement and floorplanning

We survey results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.

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Spanning Trees and Spanners

Routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of-gate, etc.) application-specific ICs (ASICs) are addressed. In previously reported works, the routing of a clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock-routing problems. The authors present a novel approach to the clock-routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions a decrease in skew with an increase in net size was proven theoretically and observed experimentally. A two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree was observed. >

Clock routing for high-performance ICs

An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described. Using sophisticated mathematical techniques, one is able to solve large problems quickly and effectively. The algorithm is very simple and elegant, making it easy to implement. In addition, it yields very good results, as is shown on a set of real examples. The algorithm was tested on the ISCAS set of logic benchmark examples using parameters for 1 mu m CMOS technology. On average , there is a 25% improvement in the wire delay for these examples compared to TimberWolf-5.6 with a small impact on the chip area. >

RITUAL: a performance driven placement algorithm for small cell ICs

An algorithm for obtaining a placement of large scale cell-based ICs subject to performance constraints is described. The problem is formulated as a constrained programming problem and is solved in two phases: continuous and discrete. Constraints are placed on total path delays including cell and interconnect delays, and the behavior of all the paths is captured. Mathematical techniques and heuristics based on Lagrangian relaxation are used to find an approximate solution to the constrained problem. The algorithm yields good results, as shown on a set of real examples. On the average, between 8% and 30% improvement in the interconnect delay of these examples is obtained with little or no impact on chip area after routing by modifying the placement alone. >

RITUAL: a performance driven placement algorithm

An algorithm was developed for the placement of small-cell ICs subject to performance constraints that is efficient in terms of speed and memory usage. The approach models wirelength using a nonlinear cost function similar to that of R.S. Tsay et al. (1988) and a timing model which uses a block-oriented representation of paths like that of M.A.B. Jackson and E.S. Kuh (1989). The timing constraints are implicitly represented using a network and nonlinear programming techniques are used to solve the wirelength minimization problem while satisfying the constraints. This allows critical paths to dynamically adjust while the placement changes to minimize wirelength. The solution of the nonlinear programming problem yields an initial placement of cells that may violate slot constraints. The authors propose hierarchical solution techniques to resolve the slot constraints. By exploiting structure inherent in the formulation, a large reduction is achieved in the number of variables that represent the problem. Additionally, developing special techniques to take advantage of the interaction between the timing model and the physical position of the cells enabled the authors to achieve a speed-up of 10-15 times over Jackson and Kuh (1989) even with a crude implementation of the algorithm. >

A fast algorithm for performance-driven placement

In this paper an algorithm is described for obtaining an initial placement of small-cell ICs subject to performance constraints. The algorithm employs an effective nonlinear wirelength function and an accurate timing model using a block-oriented representation of paths. By introducing the concept of a reduced forest of timing constraints for cap turing the structure inherent in the constraints an efficient algorithm for performance driven initial placement is developed and its finiteness proved under less stringent conditions than [JSKSO]. In addition, it does not require an initial feasible solution. The algorithm presented in [JSKSO] required an initial feasible solution, which is computationally expensive, taking over 9 hours for an example with 1418 modules. The new algorithm presented in this paper is shown to be effective on practical examples. For the example with 1418 modules, it is able to find an optimal solution in under 8 minutes of CPU time without requiring a feasible solution. Limited space necessitated a highly simplified presentation of the algorithm here. Details may be found in [SriSO].

Arvind Srinivasan

Papers

Clock routing for high-performance ICs

RITUAL: a performance driven placement algorithm for small cell ICs

RITUAL: a performance driven placement algorithm

A fast algorithm for performance-driven placement

An algorithm for performance-driven initial placement of small-cell ICs