Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

Innovative Research and Applications in Next-Generation High Performance Computing

Existing dynamic deadlock avoidance techniques have four main drawbacks: limited capability, offline avoidance algorithm, passive avoidance strategy and poor usability. To solve these problems, we propose a user-friendly, online and active avoidance technique, called Slider, to avoid multiple types of deadlocks. The key idea of Slider is that deadlocks will not happen if critical sections are executed serially. Slider interferes in thread scheduling to ensure that at any time only one thread is in the critical state. We design Slider to avoid all deadlocks except self-deadlocks caused by mutexes or rwlocks in pthread interface. We implement Slider as a pre-loadable library so that it can be applied directly to existing applications. We do four experiments to evaluate avoidance capability, performance overhead and scalability of Slider, comparing with three state-of-the-art avoidance techniques. Experimental results show Slider can correctly avoid multiple types of deadlocks in an online, active, efficient and scalable way.

Slider: an online and active deadlock avoider by serial execution of critical sections

The initiation to have a concept of shared memory in processors has built an opportunity for thread level parallelism. In various applications, synchronization or ordering tools are utilized to have an access to shared data. Traditionally, multithreaded programming models usually suggest a set of low-level primitives, such as locks, to guarantee mutual exclusion. Possession of one or more locks protects access to shared data. But, due to some flaws they become a suboptimal solution. The idea of transactional memory is in research presently as an alternative to locks. Among which, one way is hardware transactional memory. Atomicity is well supported by using transactions in hardware. In this chapter, we have focused on hardware transactional memories and the work done on them so far.

Hardware Transactional Memories: A Survey

Software transactional memory (STM) has evolved as an alternative for traditional lock-based process synchronization. It promises greater degree of concurrency and faster execution. This paper proposes a simple, lightweight, and yet efficient implementation of OFTM. The major contribution of the paper is in proposing a new STM algorithm that uses simple data structure. This does not require any contention manager toward ensuring progress condition, atomicity, and serializability of transactions besides maintaining data consistency. Experimental simulation on random data set establishes the merit of the proposed solution.

A Lightweight Implementation of Obstruction-Free Software Transactional Memory

The notion of incremental learning is to train an ANN algorithm in stages, as and when newer training data arrives. Incremental learning is becoming widespread in recent times with the advent of deep learning. Noise in the training data reduces the accuracy of the algorithm. In this paper, we make an empirical study of the effect of noise in the training phase. We numerically show that the accuracy of the algorithm is dependent more on the location of the error than the percentage of error. Using Perceptron, Feed Forward Neural Network and Radial Basis Function Neural Network, we show that for the same percentage of error, the accuracy of the algorithm significantly varies with the location of error. Furthermore, our results show that the dependence of the accuracy with the location of error is independent of the algorithm. However, the slope of the degradation curve decreases with more sophisticated algorithms

An Empirical Study of Incremental Learning in Neural Network with Noisy Training Set

The notion of incremental learning is to train an ANN algorithm in stages, as and when newer training data arrives. Incremental learning is becoming widespread in recent times with the advent of deep learning. Noise in the training data reduces the accuracy of the algorithm. In this paper, we make an empirical study of the effect of noise in the training phase. We numerically show that the accuracy of the algorithm is dependent more on the location of the error than the percentage of error. Using perceptron, feedforward neural network and radial basis function neural network, we show that for the same percentage of error, the accuracy of the algorithm significantly varies with the location of error. Furthermore, our results show that the dependence of the accuracy with the location of error is independent of the algorithm. However, the slope of the degradation curve decreases with more sophisticated algorithms.

Atrayee Chatterjee

Papers

A Lightweight Implementation of Obstruction-Free Software Transactional Memory

An Empirical Study of Incremental Learning in Neural Network with Noisy Training Set

An Empirical Study of Incremental Learning in Neural Network with Noisy Training Set