In this paper, a novel framework is presented for designing lifetime-reliable SoCs with self-adaptation capability against aging-induced degradation. The proposed flow utilizes the existing logic built-in-self-test (LBIST) hardware, and software implemented machine learning predictor to activate appropriate countermeasures to remedy the wear out in the field. Using an innovative method, we convert ATPG-generated transition delay test patterns into LBIST patterns to activate high-usage critical/near-critical paths in-field, and the corresponding responses are utilized in developing the predictor. A gate-overlap and path-delay-aware algorithm selects the optimum set of patterns. The area and test time overhead for the framework are very low. We implemented our proposed flow on SoC benchmark designs, and the results demonstrated its efficacy.

Design of Reliable SoCs With BIST Hardware and Machine Learning

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

Level shifter, digital-to-analog converter, and buffer amplifier, and source driver and electronic device including the same

In this paper, we present a novel methodology, BIST-RM, to accurately predict the degradation due to aging mechanisms in a SoC at run-time by utilizing the existing LBIST hardware and software implemented Machine Learning classifier. Using an innovative method, we convert ATPG-generated transition delay patterns into LBIST patterns, and the corresponding responses are utilized in developing the predictor. A gate-overlap and path delay-aware pattern selection algorithm selects the features for the classier. Using clock sweeping, LBIST is able to capture the aging effect on targeted paths. The result of machine learning is then utilized to activate countermeasures to remedy the degradation in the field. The area and test time overhead are very low. We implemented our proposed flow on SoC benchmark circuits, and the results demonstrated worst-case prediction accuracy of 94% to 97%.

BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Integrated circuit device body bias circuits and methods

Process monitors that independently sense on-die PMOS and NMOS as-fabricated performance are presented. The monitors provide digital outputs, making them easily integrated blocks on SOC designs. We present two monitor approaches, one primarily analog and one primarily digital, applied to both logic circuits and SRAM, which may require different optimal body biases for best operation. The monitors correctly sense the die as-fabricated process corners on 55-nm test die, demonstrated on FF, FS, TT, SF SS corner skew lots. Experimentally measured performance and power correction is demonstrated for digital circuits, as well as parametric yield correction for SRAMs. Logic ring oscillators demonstrate 74% reduction in standard deviation for delay and leakage with monitor specified body biases. Similar improvement is demonstrated on embedded microprocessors. Finally, 55% and 72% reduction in SRAM read current variability and leakage, respectively, is also shown.

Independent N and P process monitors for body bias based process corner correction

An integrated circuit can include a plurality of drive monitoring sections, each including at least one transistor under test (TUT) having a source coupled to a first power supply node, a gate coupled to receive a start indication, and a drain coupled to a monitor node, at least one monitor capacitor coupled to the monitor node, and a timing circuit configured to generate a monitor value corresponding to a rate at which the TUT can transfer current between the monitor node and the first power supply node; and a body bias circuit configured to apply a body bias voltage to at least one body region in which at least one transistor is formed; wherein the body bias voltage is generated in response to at least a plurality of the monitor values.

Body bias circuits and methods

A process monitor based on slew-rate measurement has been applied to a body bias control system to detect the process corners and adjust the body bias voltage necessary to meet the power and performance requirements for CMOS circuits. The process monitor consists of N- and P- type slew generators, pulse generator, pulse extender, counter and control circuits. A new analog pulse extender has been developed to increase the pulse width for easy characterization of process corners in practical systems. Circuit description, design considerations, and measured results of the process monitor and body bias generator circuits in 55nm CMOS process are presented. Active circuit area for the process monitor and body bias generator are 0.023 mm2 and 0.013 mm2 and power dissipation for process monitor and bias generator are 400 μW and 55 μW using a 0.9 V supply. Measured silicon results match with simulation results and show correct operation of the circuits.

A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications

An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Slew based process and bias monitors and related methods

An integrated circuit device can include at least a first bi-directional biasing circuit having a first substrate portion containing a plurality of first transistors; a first control digital-to-analog converter (DAC) to generate any of a plurality of first target values in response to a first target code; a first detect circuit configured to generate a difference value between the first target values and a first limit value; and at least a first charge pump circuit configured to drive the first substrate portion between a forward body bias voltage and a reverse body bias voltage for the first transistors in response to first target values. Embodiments can also include a performance monitor section configured to determine a difference between the voltage of the first substrate portion and a target voltage. Control logic can generate first code values in response to the difference between the voltage of the first substrate portion and the target voltage. Methods are also disclosed.

Augustine Kuo

Papers

Body bias circuits and methods

A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications

Integrated circuit device body bias circuits and methods

Slew based process and bias monitors and related methods

Circuits and devices for generating bi-directional body bias voltages, and methods therefor