This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.

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System-level power optimization: techniques and tools

We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation.We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory (DRAM). We end with memory addressing related issues.

Data and memory optimization techniques for embedded systems

Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold (NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper, we describe the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multicore clusters. We introduce instruction extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure toward the shared-memory hierarchy. For typical data-intensive sensor processing workloads, the proposed core is, on average, $3.5\times $ faster and $3.2\times $ more energy efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. Single Instruction Multiple Data extensions, such as dot products, and a built-in L0 storage further reduce the shared-memory accesses by $8\times $ reducing contentions by $3.2\times $ . With four NT-optimized cores, the cluster is operational from 0.6 to 1.2 V, achieving a peak efficiency of 67 MOPS/mW in a low-cost 65-nm bulk CMOS technology. In a low-power 28-nm FD-SOI process, a peak efficiency of 193 MOPS/mW (40 MHz and 1 mW) can be achieved.

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

A wireless electrostimulation system can comprise a wireless energy transmission source, and an implantable cardiovascular wireless electrostimulation node. A receiver circuit comprising an inductive antenna can be configured to capture magnetic energy to generate a tissue electrostimulation. A tissue electrostimulation circuit, coupled to the receiver circuit, can be configured to deliver energy captured by the receiver circuit as a tissue electrostimulation waveform. Delivery of tissue electrostimulation can be initiated by a therapy control unit.

Wireless tissue electrostimulation

A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.

Macroscalar processor architecture

Power consumption analyzes of embedded processors indicate that a significant amount of power is consumed in accessing memory and in the control path. Based on this, and on the runtime characteristics of signal processing applications, we advocate the use of instruction buffering as a power-saving technique for processors for signal processing and multimedia applications. Two approaches, a decoded instruction buffer (DIB) and a decoded instruction cache, are considered. Performance improvements in representative applications in speech processing such as, the vector sum excited linear prediction (VSELP), linear prediction coding coefficient computation (LPC), and two-dimensional 2-D 8/spl times/8 DCT which is used in image compression, are provided. The reduction in power obtained is between between 25 and 30%.

Instruction buffering to reduce power in processors for signal processing

The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.

Method and apparatus for reducing the power consumption in a programmable digital signal processor

A repeat-bit based system and method for executing zero overhead loops, or repeat loops, in an information processing chip that does not require a repeat end register or a dedicated comparator. Executing repeat loops requires a processor to iterate N times a code fragment of loop instructions. All systems providing this capability must know when to refetch the first loop instruction at the end of a repeat. To do this, the present invention adds a repeat bit to the processor's instruction set. This bit is set by the assembler/compiler that generates the executable code fragment comprising the repeat loop. Where the repeat loop includes plural instructions, the assembler sets the repeat bit of the penultimate loop instruction. As each loop instruction is fetched, decoded and executed, the decoder detects the repeat bit and passes it to loop control circuitry. If the code fragment has not been iterated N times and the repeat bit is set, the program counter (PC) is loaded with the address of the first repeat loop instruction, which is refetched. Otherwise, the PC is incremented and the next instruction is fetched. Where the repeat loop has a single instruction, a nop instruction must be added after the instruction to be repeated. Two systems and methods for maintaining the repeat count are disclosed. The first requires a decrementor that decrements the repeat count from N each time the loop is iterated. Another replaces the decrementor with the PC incrementor, which increments the repeat counter from -N or -(N-1).

Repeat-bit based, compact system and method for implementing zero-overhead loops

A method and apparatus for re-generating debug commands is provided comprising a source program having embedded debug commands in a first distinguishable field, and an assembler. The assembler operates on the source code extracting the embedded debug commands and associated address information from the source code while generating object code. The debug commands are stored in a command file for use during simulation. A simulator executes the assembled object code in conjunction with a debugger which executes the stored debug commands as designated during the execution cycle. Upon the termination of a simulation run and the subsequent modification of the source program, the debug commands are automatically re-generated with correct addresses as determined during the subsequent assembly. When the edited source file is loaded, the break-points are cleared and a new command file is executed to insure that the break-points are relocated to the correct source lines. The execution of the embedded debug commands can be enabled or disabled by means of a command line option, so when the debugging is complete, the debug information will not be outputted.

Embedded debug commands in a source file

A system and method that implement a butterfly operation for a fast fourier transform operation in a processor using a matrix-vector-multiply instruction. A first set of inputs to the butterfly operation are defined as r1+j i1 and r2+j i2, and a twiddle factor Wn is defined as Wn=e−j2π/N=cos(2π/N)−j sin(2π/N)=a+jb. The butterfly operation stores r1, i1, r2 and i2 in a first set of registers and stores the twiddle factor in matrix registers. The matrix-vector-multiply instruction is executed between the matrix registers and the first set of registers.

Avadhani Shridhar

Papers

Instruction buffering to reduce power in processors for signal processing

Method and apparatus for reducing the power consumption in a programmable digital signal processor

Repeat-bit based, compact system and method for implementing zero-overhead loops

Embedded debug commands in a source file

System and method for performing a fast fourier transform using a matrix-vector multiply instruction