The present invention relates to a testing tool for testing of complex software systems having a plurality of interrelated system components and a suite of test scenarios for testing the performance of the plurality of interrelated system components. The testing tool includes an Automated Multidimensional Traceability Matrix system for determining linkages between interrelated system components, a means for identifying a change in one or more of the interrelated system components, a means for applying the Automated Multidimensional Traceability Matrix, a means for executing all of or a subset of the test scenarios associated with the interrelated system components that may be affected by the change and a means for evaluating the results of the executed test scenarios.

Testing tool comprising an automated multidimensional traceability matrix for implementing and validating complex software systems

A device and a method are provided for increasing processing speed and for ensuring system security when an application or a driver is added. The device includes a first CPU group that executes software composed of basic processing and an OS; a second CPU group that executes software composed of additional processing and OS corresponding to the additional processing, inter-processor communication means used for communication between the first CPU and the second CPU, and access control means that controls access made by the second CPU to a memory and/or an input/output device.

Information communication device and program execution environment control method

A priority register is provided for each of a multiple processor cores of a chip multiprocessor, where the priority register stores values that are used to bias resources available to the multiple processor cores. Even though such multiple processor cores have their own local resources, they must compete for shared resources. These shared resources may be stored on the chip or off the chip. The priority register biases the arbitration process that arbitrates access to or ongoing use of the shared resources based on the values stored in the priority registers. The way it accomplishes such biasing is by tagging operations issued from the multiple processor cores with the priority values, and then comparing the values within each arbiter of the shared resources.

Priority registers for biasing access to shared resources

A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.

Processor Cluster Architecture and Associated Parallel Processing Methods

A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.

Register set used in multithreaded parallel processor architecture

A resource negotiation technique and apparatus which streamlines arbitration for access to a shared resource by centralizing arbitration for groups of shared resources such as control registers into an access register An accessing agent first writes a request to an appropriate bit of a resource negotiation register (RNR), and then reads back a grant status If the request for access to the shared resource is not successful in the first attempt, the requesting processor may continuously read the grant status until it is successful Alternatively, the resource negotiation register may cause an interrupt in the requesting processor upon grant of access to the shared resource A logic level indicating that access is denied generally indicates that another processor in the multi-processor system is currently granted access to the corresponding shared resource Once the processor requesting permission for writing to the shared resource has been granted permission, that winning processor is expected to complete its access to the shared resource, and then indicate back to the shared resource negotiator that access is no longer required, eg, by clearing the corresponding request bit

System for negotiating access to a shared resource by arbitration logic in a shared resource negotiator

A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.

Shared devices and memory using split bus and time slot interface bus arbitration

A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus. In an adaptive arbitration mode, the subordinate arbiter combines static time slot information assigned in configuration registers together with actual bus requests to generate grant signals to the requesting devices, and reassigns all or portions of time slots which, although assigned to a particular device, are left unused for the relevant system cycle. A historical buffer may be maintained for any or all time slots. Using this historical information, long term statistical information may be generated. Moreover, the master controller may re-tune time slot configurations based on the historical information regarding past recent use of the relevant time slots.

Programmable time slot interface bus arbiter

A time division multiplexing (TDM) method and apparatus for interfacing data from communication channels to a TDM bus. The TDM arrangement uses a shift register to control a tri-state buffer. The shift register regulates the tri-state buffer based on a data bit pattern loaded into the shift register. The data bit pattern corresponds to the status of the individual channels. Each channel is assigned a bit which indicates whether the channel is active or inactive. As the shift register shifts out data, the tri-state buffer allows data to flow onto the TDM bus when a bit indicating an active channel is present and insulates the TDM bus from the communication channels when a bit representing an inactive channel is present. A processor is used to control the interrelationship of the multiple communication channels and to generate the status bits to be loaded into the shift register. The processor fills the shift register through the use of a storage register. In a preferred embodiment, the shift register is capable of shifting out a sufficient number of bits to fill an entire transmission frame operating in T1 (24 channels), E1 (32 channels), 64-slot (64 channels), and 128-slot (128 channels) transmission modes. In addition, the tri-state buffer may perform the additional function of level shifting the voltage level of the data from the multiple communication channels to a level compatible with the TDM bus.

Avinash Velingker

Papers

System for negotiating access to a shared resource by arbitration logic in a shared resource negotiator

Shared devices and memory using split bus and time slot interface bus arbitration

Programmable time slot interface bus arbiter

Method and apparatus for interfacing multiple communication devices to a time division multiplexing bus

Hierarchical bus arbitration