Redundancy identification is a challenging open problem in logic optimization of Boolean circuits. Partitioning techniques are employed successfully to solve the redundancy identification problem with less time and higher scalability. Any heuristic/algorithm for the Logic optimization problem, and hence the redundancy identification problem is compute-intensive, especially when very high approximation to the optimal solution is demanded. This is because the problems are NP-complete. This necessitates parallel heuristics/algorithms to speed-up the computation process. In this paper, we present a parallel partitioning approach for the logic optimization problem using the concept of redundancy identification. This result finds extensive applications in the area of VLSI CAD tool design.

Parallel partitioning techniques for logic minimization using redundancy identification

This paper discusses the technology mapping problem on Hybrid Field Programmable Architectures (HFPA). HFPAs are realized using a combination of the following programmable logic devices, namely, Lookup Tables (LUTs) and Programmable Logic Arrays (PLAs). The HPFAs provide the designers with the advantages of both LUT-based Field Programmable Gate Arrays and PLAs. Specifically, use of PLAs can result in reduction of area required for mapping a circuit. Designing a methodology that maps a given circuit on to the HFPA that exploits the above-mentioned advantages to the maximum is a problem of very great research and commercial interest. This paper presents the SHAPER, which maps the circuits onto HFPAs using reconvergence analysis. Empirically, it is shown that SHAPER yields 18% better area-reduction than the previous known algorithms.

SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis

With the increasing non-recurring engineering cost of advanced process technologies, reconfigurable devices have received great attention in small and medium-volume integrated circuit designs. However, low logic diversity and slow timing performance limit the efficacy of field-programmable gate array (FPGA) and complex programmable logic device (CPLD). In this paper, we propose an efficient hybrid lookup table (LUT)/ sum-of-product (SOP) reconfigurable design style that exploits the advantages of circuit designs for both LUT cells and SOP cells. Then, architectural evaluations are performed to achieve the best cell ratio. Based on this architecture, we propose an efficient methodology for hybrid LUT/SOP logic synthesis that employs SOP-cell transformation, phase flipping, and phase duplication. The experimental results demonstrate that our proposed hybrid LUT/SOP design style achieves 35% circuit performance improvement and 52% transistor count reduction compared to the depth optimal 4-LUT-based FPGA. In comparison with the CPLD, our hybrid design style requires only 11% of the transistor count and reduces circuit delay by 11%.

http://nthucad.cs.nthu.edu.tw/~yyliu/paper/2014_JISE_hybridmap.pdf

Hybrid LUT and SOP reconfigurable architecture

This work discusses the technology mapping problem on hybrid field programmable architectures (HFPA). HFPAs are realized using a combination of lookup tables (LUTs) and programmable logic arrays (PLAs). HFPAs provide the designers with the advantages of both LUT-based field programmable gate arrays (FPGA) and PLAs. Specifically, the use of PLAs leads to reduced area in mapping the given circuit. Designing of technology mapping methodologies which map a given circuit on to the HFPA that exploits the above-mentioned advantages is a problem of great research and commercial interest. This work presents SHAPER, which maps the circuits onto HFPAs using reconvergence analysis. Empirically, it is shown that SHAPER yields better area-reduction than the previous known algorithms.

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis

Summary form only given. Modern day field programmable gate arrays (FPGA) include in addition to look-up tables, reasonably big configurable embedded memory blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. We present a methodology to utilize such unused EMBs as large look-up tables to map multioutput combinational subcircuits of the application, with depth minimization as the main objective along with area minimization in terms of the number of LUTs used. Depth minimization is an important goal while mapping performance driven circuits. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, leads to up to 14% reduction in depth when compared with the DAG-map algorithm, along with comparable reduction in area.

B. Jayaram

Papers

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis

SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis

MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays