In combination with a wheel for a bicycle and the like having an annular rim, a hub rotatable about its axis, and axially offset groups of circumferentially spaced spokes which centrally support the hub on the rim; a wheel decorating ornament comprising an annular, planar sheet of material decorated on opposite sides, axially disposed between the groups of spokes and radially disposed between the rim and the hub.

The Test Access Port and Boundary Scan Architecture

The issues of printed circuit board (PCB) interconnect testing are addressed in the context of boundary-scan architecture. Boundary-scan architecture is treated here as the framework for a PCB level built-in self-test (BIST). A novel BIST method is developed which utilizes various features of the architecture. Boundary-scan architecture is shown to have the capability to generate time-efficient test vector sets. Response compaction within the boundary-scan chain is introduced to reduce shift out time as well as to simplify detection and diagnosis. However, the proposed BIST schemes require some extensions of the standard boundary-scan cells, and the schemes can work only if every boundary-scan cell of every IC on the PCB has the proposed extensions. >

BIST of PCB interconnects using boundary-scan architecture

Previous work on the diagnosis of faults in a wiring network has been based on the assumption that both open and short faults do not exist on the same net. When this assumption is relaxed, these results fail to identify all diagnosable faults. The non-diagnosability of these faults, including shorts between nets, represents a deficiency. In this paper we analyze and explain the causes for this deficiency. In addition, we provide new theoretical results and test algorithms, and show how these deficiencies can be overcome. A test set, which is generated based on these results, can identify all diagnosable faults in a wiring network with arbitrary open and short faults. Two adaptive diagnosis algorithms are also presented which can reduce the number of test vectors while retaining the same level of diagnostic resolution. Another algorithm that can reduce the number of vectors by exploring the structure information of the network is also presented.

Maximal diagnosis for wiring networks

The paper presents a methodology for the simulation of massive number of device-level transient faults. Fault injection locations and the gate around those locations are extracted and evaluated with SPICE. The extracted sub-circuits are exercised exhaustively while fault-injections are performed. Faulty behavior at the outputs of each sub-circuit is recorded in a dictionary, along with the associated input vector, fault-injection time, and location. The recorded logical errors are injected concurrent transient simulator is developed to allow simultaneous evaluation of a massive number of fault-injections, in a single simulation pass. The methodology is illustrated by a case study of MC68000 microprocessor.

Fault behavior dictionary for simulation of device-level transients

A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution.

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A boundary scan test controller for hierarchical BIST

The authors propose test schemes for glue logic (non-boundary-scan components) interconnects. Testing these interconnects is difficult owing to reduced accessibility and glue-logic function-dependent outputs. The proposed schemes address these testability issues and provide efficient boundary-scan based techniques. The tests are applied under the B-Scan DFT (design-for-testability) environment as scan tests. Thus, issues such as ease of test vector generation, test vector loading time, and test application time are very important for the proposed schemes. The application of the test schemes is described. >

B.N. Dostie

Papers

Testing of glue logic interconnects using boundary scan architecture