As the Internet of Things (IoT) is relying on the exchange of information, this research work progress through analyzing the radio frequency identification, which is an emerging technology and one of the most critical technologies in the current computing world. This emerging technology can find its applications in various fields ranging from healthcare, construction, smart shopping, hospitality to transportation and many more. This research work focuses on generating a bill for the shopping cart. The main idea is to save customers time by providing digital billing system with which the customers can get the bill through their registered Email. A compartment of all the products will be attached with RFID tags/cards, and the purchasing product information will get stored in the database. The billing will then get generated in the LCD as well as the server. This system shows how RFID technology will make life easier and secured and helpful in the future. This system describes IoT by mainly concentrating on its utilization towards improving and ensuring the future shopping.

Smart Cart Shopping System with an RFID Interface for Human Assistance

The electronics devices are facing a foremost drawback of standby leakage, which will severely impact the electronics industry from the past few decades. As well as the need for cache memory is proportionately increasing with the data processing frequency of the processors. SRAM is also used for cache reminiscence layout. Many low-energy techniques are considered to minimize the current leakage. Full MOSFET 6T SRAM mobile is the main application used for designing the digital circuits. This task implements 6T MOSFET SRAM cell. The FinFET spectra models, layout, and circuit level software implementations are carried out using FinFET 18nm nodes. The power intake, mainly off-state leakage, present-day, is the every other major problem that is being confronted inside the present-day technology of electronic enterprise because of the increasing chip densities with a wider variety of transistors. Energy consumption is the fundamental disadvantage in the SRAM model evaluation. Considering the salient features of the FinFET, 6T SRAM cell is designed at 18nm FinFET spectre models, and it is compared in contrast to MOSFET standard cell in support to the simulation results.

6Transistor SRAM Cell designed using 18nm FinFET Technology

Shift registers are utilized in personal computer systems as an element of ability, including RAM and numerous types of registers. Besides, automatic framework tasks including splitting, duplicating, and so forth are used to convert the identical information into sequential data or vice versa. This article provides a comprehensive shift register that can play a consistent and consistent shift activity. When the device limit is reduced after direct guidance, the short channel acts as power loss, surface scattering, and sinking speed. The recently planned relocation register uses CMOS, which will consume more power. The proposed registry, which takes advantage of the main innovations of FinFET, has the power to eliminate or alleviate the difficulties mentioned above. Relative performance studies are completed more rapidly than other standard schemes, taking into account necessary performance measures such as power delay product (PDP) and element energy delay product (EDP) measurements.

Universal Shift Register Designed at Low Supply Voltages in 15 nm CNTFET Using Multiplexer

In this paper, we propose a system that will analyze the speech signals and gather the emotion from the same efficient solution based on combinations. This system solely served to identify emotions present in the signal or speech using concepts of deep learning and algorithms of machine learning (ML). Using the above mentioned, the system will determine the eight emotions present in the speech signal; anger, sad, happy, neutral, calm, fearful, disgust and surprised. The system is built with the language python and librosa, sound file libraries, which are part of the more extensive scikit library used for specific applications of audio analysis. The system will receive the sound files from the dataset present on the internet called RAVDESS. It will then analyze the audio files' spectrograms in WAV format and return us the efficiency of the system, which is the intended Outcome. We have achieved an efficiency rate of 81.82%.

Speech Emotion Recognition System With Librosa

VLSI technology is essential for chip fabrication, and 3 to 8 decoder circuits are used in electronic gadgets; consistency of design, small, fast, in this proposed circuit, 3 to 8 decoder is implemented using 20nm CNTFET technology. 3 to 8 decoders are the key segments in some real-time applications. For the most recent couple of years, the minuscule size of MOSFET, which is under many nanometers, made some operational issues, for example, expanded entryway oxide leakage, intensified intersection leakage, high sub-limit conduction. The proposed model is recreated utilizing Cadence virtuoso with 20nm CNTFET nodes.

Energy Efficient Decoder Circuit Using Source Biasing Technique in CNTFET Technology

The limitation of CMOS to operate under 25nm is a major concern, which is viewed in this paper. Also, scaling issues like leakage current, lower carrier mobility, higher junction capacitance limits the transistor operation is discussed. At lower voltage values, CMOS productive decreases drastically, which reflects on the performance of the circuit to achieve its criteria’s. In the present-day scenario of electronic industry, the speed of the processor is increasing, the urge for speed cache memory is also increasing. In cache memory design, SRAM cell is mainly used, CMOS SRAM Cells are producing more delay and also limitations like mentioned above. Therefore, an alternative preferred choice for SRAM Cells is FinFET, which increases the speed of the Cell by avoiding limitations caused by the bulk CMOS. By considering the advantages of the FinFET, SRAM Cells are implemented in Cadence virtuoso using FinFET 18nm Spectre. In this paper, standard SRAM Cells like 7T, 8T, 9T, and 1oT are simulated and parameters like power, delay, power delay product (PDP), energy-delay product (EDP) are calculated and respective values are presented by varying the voltage (V). SRAM Cells behavior under different voltages is graphically represented. CMOS SRAM Cell values have been taken from previous works of SRAM. By comparing the parameters, a drastic increase in the speed of the FinFET SRAM Cells can be observed over CMOS SRAM Cells.

Comparative Validation of SRAM Cells Designed using 18nm FinFET for Memory Storing Applications

Compressors are the essential supplements of Full adders and half adder in any multiplier design. Compressors play a vital role in reducing delay and increasing the overall performance of a multiplier. In this paper, various compressors such as 5:3, 10:4, 15:4 and 20:5 are designed and implemented in Cadence virtuoso tool at 180nm technology. Later on, the compressor was designed using FinFET technology. The designs in both technologies were simulated, and their performance was compared. Simulation analysis depicts that the compressor designed in FinFET technology will show less power consumption than CMOS technology.

B. Sadgurbabu

Papers

Comparative Validation of SRAM Cells Designed using 18nm FinFET for Memory Storing Applications

Design and Implementation of Low power FinFET based Compressor