An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Methods and displays utilize row and column drivers with ZnO channels that control pixel transistors with ZnO channels, which in turn address OLEDs of an array to produce images of a display screen. A display backplane including the ZnO row and column drivers and the OLEDs may be constructed by utilizing aperture masking or a combination of photolithography and aperture masking. Monolithic integration of the ZnO row and column drivers together with the ZnO pixel transistors is thereby achieved.

Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes

Ab initio density functional theory calculations are performed to study the electronic properties of a MoS${}_{2}$ monolayer deposited over a SiO${}_{2}$ substrate in the presence of interface impurities and defects. When MoS${}_{2}$ is placed on a defect-free substrate, the oxide plays an insignificant role since the conduction band top and the valence band minimum of MoS${}_{2}$ are located approximately in the middle of the SiO${}_{2}$ band gap. However, if Na impurities and O dangling bonds are introduced at the SiO${}_{2}$ surface, these lead to localized states, which modulate the conductivity of the MoS${}_{2}$ monolayer from $n$- to $p$-type. Our results show that the conductive properties of MoS${}_{2}$ deposited on SiO${}_{2}$ are mainly determined by the detailed structure of the MoS${}_{2}$/SiO${}_{2}$ interface, and suggest that doping the substrate can represent a viable strategy for engineering MoS${}_{2}$-based devices.

http://www.tara.tcd.ie/bitstream/handle/2262/66701/PhysRevB.87.165402.pdf;sequence=1

Origin of the n-type and p-type conductivity of MoS2 monolayers on a SiO2 substrate

A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.

Planarization using plasma oxidized amorphous silicon

Solid Electrolyte Interphase on Native Oxide-Terminated Silicon Anodes for Li-Ion Batteries

1: Semiconductor Crystals. 1.1. Crystals and Crystallographic Orientations. 1.2. The Silicon Crystal. 1.3. Wafer Preparation. 1.4. Compound Semiconductors. 2: Thermal Oxidation and Nitridation. 2.1. SiO2 and SiO2-Si Interface. 2.2. Thermal Oxidation. 3: Thin Film Deposition. 3.1. Chemical Vapor Deposition. 3.2. Chemical-Physical Deposition Processes. 3.3. Physical-Vapor Deposition. 4: Lithography. 4.1. Optical Lithography. 4.2. Resolution Enhancement Techniques. 4.3. Electron-Beam Lithography. 4.4. X-Ray Lithography. 4.5. Ion-Beam Lithography. 5: Contamination Control and Etch. 5.1. Clean Processes. 5.2. Etching. 6: Ion Implantation. 6.1. Principle of Operation. 6.2. Energy Loss and Range Distribution. 6.3. Crystal Damage and Dopant Activity. 7: Diffusion. 7.1. Point Defects. 7.2. Fick's Laws. 7.3. Non-Constant Diffusivity. 7.4. Diffusion in Polysilicon. 7.5. Diffusion in Insulators. 7.6. Diffusion Sources. 7.7. Gettering in Silicon. 8: Contact and Interconnect Technology. 8.1. Contact Metallurgy. 8.2. Poly-Metal Dielectrics. 8.3. Metal Interconnects. 8.4. Inter-Level Dielectrics. 8.5. Multi-Level Metals. 8.6. Reliability Considerations. Subject Index.

Badih El-Kareh

Papers

Fundamentals of Semiconductor Processing Technology