International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

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Design Of Analog Cmos Integrated Circuits

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

Pesticides are one of the major inputs used for increasing agricultural productivity of crops. The pesticide residues, left to variable extent in the food materials after harvesting, are beyond the control of consumer and have deleterious effect on human health. The presence of pesticide residues is a major bottleneck in the international trade of food commodities. The localization of pesticides in foods varies with the nature of pesticide molecule, type and portion of food material and environmental factors. The food crops treated with pesticides invariably contain unpredictable amount of these chemicals, therefore, it becomes imperative to find out some alternatives for decontamination of foods. The washing with water or soaking in solutions of salt and some chemicals e.g. chlorine, chlorine dioxide, hydrogen peroxide, ozone, acetic acid, hydroxy peracetic acid, iprodione and detergents are reported to be highly effective in reducing the level of pesticides. Preparatory steps like peeling, trimming etc. remove the residues from outer portions. Various thermal processing treatments like pasteurization, blanching, boiling, cooking, steaming, canning, scrambling etc. have been found valuable in degradation of various pesticides depending upon the type of pesticide and length of treatment. Preservation techniques like drying or dehydration and concentration increase the pesticide content many folds due to concentration effect. Many other techniques like refining, fermentation and curing have been reported to affect the pesticide level in foods to varied extent. Milling, baking, wine making, malting and brewing resulted in lowering of pesticide residue level in the end products. Post harvest treatments and cold storage have also been found effective. Many of the decontamination techniques bring down the concentration of pesticides below MRL. However, the diminution effect depends upon the initial concentration at the time of harvest, substrate/food and type of pesticide. There is diversified information available in literature on the effect of preparation, processing and subsequent handling and storage of foods on pesticide residues which has been compiled in this article.

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Effect of handling and processing on pesticide residues in food- a review

Cognitive radio technology has the potential to address the shortage of available radio spectrum by enabling dynamic spectrum access. Since its introduction, researchers have been working on enabling this innovative technology in managing the radio spectrum. As a result, this research field has been progressing at a rapid pace and significant advances have been made. To help researchers stay abreast of these advances, surveys and tutorial papers are strongly needed. Therefore, in this paper, we aimed to provide an in-depth survey on the most recent advances in spectrum sensing, covering its development from its inception to its current state and beyond. In addition, we highlight the efficiency and limitations of both narrowband and wideband spectrum sensing techniques as well as the challenges involved in their implementation. TV white spaces are also discussed in this paper as the first real application of cognitive radio. Last but by no means least, we discuss future research directions. This survey paper was designed in a way to help new researchers in the field to become familiar with the concepts of spectrum sensing, compressive sensing, and machine learning, all of which are the enabling technologies of the future networks, yet to help researchers further improve the efficiently of spectrum sensing.

https://www.mdpi.com/1424-8220/19/1/126/pdf/1

A Comprehensive Survey on Spectrum Sensing in Cognitive Radio Networks: Recent Advances, New Challenges, and Future Research Directions

Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers. This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. We present a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption . Categories and Subject Descriptors VHDL, Behavioural modeling, General Terms Carry select adder, multiple stage adder Keywords Adder, Carry select Adder, carry skip adder, VHDL Simulation 1. INTRODUCTION compact Addition usually impacts widely the overall performance of digital systems and a crucial arithmetic function. In electronic applications adders are most widely used. Applications where these are used are multipliers, DSP to execute various algorithms like FFT, FIR and IIR. Wherever concept of multiplication comes adders come in to the picture. As we know millions of instructions per second are performed in microprocessors. So, speed of operation is the most important constraint to be considered while designing multipliers. Due to device portability miniaturization of device should be high and power consumption should be low. Devices like Mobile, Laptops etc. require more battery backup. So, a VLSI designer has to optimize these three parameters in a design. These constraints are very difficult to achieve so depending on demand or application some compromise between constraints has to be made. Ripple carry adders exhibits the most compact design but the slowest in speed. Whereas carry lookahead is the fastest one but consumes more area [2]. Carry select adders act as a compromise between the two adders. In 2002, a new concept of hybrid adders is presented to speed up addition process by Wang et al. that gives hybrid carry look-ahead/carry select adders design [7]. In 2008, low power multipliers based on new hybrid full adders is presented in [8]. In 2008, Hasan Krad et al provided the performance analysis for a 32-Bit Multiplier with a Carry look-ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL and showed that CLA multiplier is almost double in speed as compared to RCA multiplier [9]. The rest of the paper is organized as follows. In section 2, a brief about ripple carry adder, carry skip and variable carry skip is given. In the same section carry select adder is introduced along with partitioning methodology. Also a new architecture with clock sharing is introduced. Section 3 provides the results obtained. Section 4 concludes the paper

/pdf/improved-carry-select-adder-with-reduced-area-and-low-power-4vekc9icki.pdf

Improved Carry Select Adder with Reduced Area and Low Power Consumption

In this paper, design of two different array multipliers are presented, one by using carry-look-ahead (CLA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).

Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look- Ahead Adder

This paper proposes a low power Linear Feedback Shift Register (LFSR) for Test Pattern Generation (TPG) technique with reducing power dissipation during testing. The correlations between the consecutive patterns are higher during normal mode than during testing. The proposed approach uses the concept of reducing the transitions in the test pattern generated by conventional LFSR. The transition is reduced by increasing the correlation between the successive bits. The simulation result show that the interrupt controller benchmark circuit's testing power is reduced by 46% with respect to the power consumed during the testing carried by conventional LFSR.

Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST

This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. Further, we present a design methodology of hybrid carry lookahead/carry skip adders (CLSKAs). This modified carry skip adder is modeled by using both fix and variable block size. In conventional carry skip adder, each block consists of ripple carry adder and skip logic is used after each block to generate carry for next block. The speed of operation depends on carry propagation from previous block to next block. In CLSKAs, we use carry lookahead logic in each block to generate carry for next block. The modified carry skip adders presented in this paper provides better speed and power consumption as compare to conventional carry skip adder and other adders like ripple carry adder, carry lookahead adder, Ling adder, carry select adder. The modified carry skip adders with fix block require few more CLB’s because of Carry lookahead logic, whereas with variable block scheme, area optimization is achieved.

Performance Analysis of Fast Adders Using VHDL

Nowadays, Vending Machines are well known among Japan, Malaysia and Singapore. The quantity of machines in these countries is on the top worldwide. This is due to the modern lifestyles which require fast food processing with high quality. This paper describes the designing of multi select machine using Finite State Machine Model with Auto-Billing Features. Finite State Machine (FSM) modelling is the most crucial part in developing proposed model as this reduces the hardware. In this paper the process of four state (user Selection, Waiting for money insertion, product delivery and servicing) has been modelled using MEALY Machine Model. The proposed model is tested using Spartan 3 development board and its performance is compared with CMOS based machine.

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Balwinder Singh

Papers

Improved Carry Select Adder with Reduced Area and Low Power Consumption

Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look- Ahead Adder

Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST

Performance Analysis of Fast Adders Using VHDL

Finite State Machine based Vending Machine Controller with Auto-Billing Features