Circuit configurations for a high power switch-mode voltage regulator circuit is disclosed that include an array of Metal Oxide Semiconductor (MOS) switching transistors electrically coupled to one another at their drains and sources and a plurality of gate driver circuits. Each gate driver circuit is coupled to a gate and dedicated to driving only one MOS switching transistor.

Method and apparatus for high performance switch mode voltage regulators

A switching voltage regulator includes a switching transistor (MP1) connected to conduct a current (i) between a supply voltage (Vdd) and a first node (5.0.) in response to a control signal which cycles the transistor (MP1)and off, and a “pre-driver” circuit (62)which provides the control signal. The control signal is pulled up and down with a current Idrv. The per-driver circuit adaptively varies Idrv such that it is at a relatively low level when the rate of change of current I (di/dt) in the switching transistor (MP1) is relatively high, and is at a relatively high level when di/dt is relatively low.

Self-timed switching regulator pre-driver

The present invention discloses an output driver circuit providing linear I/V characteristics, i.e. constant output impedance, during output voltage transitions. The output driver circuit includes a first input transistor, a second input transistor, a first pair of transistors, a second pair of transistors, a first output transistor and a second output transistor. The first input transistor inputs a first input signal and has an output node coupled to the output node of the output driver circuit. The second input transistor inputs a second input signal and has an output node coupled to the output node of the output driver circuit. The first pair of transistors is responsive to a first control signal and the output signal for generating a second control signal. The second pair of transistors is responsive to a third control signal and the output signal for generating a fourth control signal. The first output transistor is operative to receive the second control signal and has an output node coupled to the output node of the output driver circuit. The second output transistor is operative to receive the fourth control signal and has an output node coupled to the output node of the output driver circuit.

MOS output driver circuit with linear I/V characteristics

A large pull-down voltage-output-low VOL transistor is placed in parallel with a smaller pull-down switching transistor. The smaller switching pull-down transistor is turned on during switching. Once switching has nearly completed, the larger pull-down VOL transistor is turned on to provide a current sink for maintaining a VOL close to ground. Switching current is limited by the smaller switching pull-down transistor, while a large static sink current is provided by the VOL transistor to meet VOL requirements. The gate of the VOL transistor is controlled by p-channel and n-channel data transistors that are controlled by the data input, and p-channel and n-channel feedback transistors with gates connected to the buffer output. An upper n-channel transistor provides current to an intermediate node at the drain of the p-channel feedback transistor, keeping it near an intermediate voltage.

Reduced-undershoot CMOS output buffer with delayed VOL-driver transistor

The circuit configuration compensates runtime and pulse-duty-factor differences of two input signals having approximately equal frequency and phase. For each input signal respectively present at an input of the circuit configuration, a signal path is provided that, dependent on the state of the output, is influenced in such a way that the output signal follows the input signal that changes first. A feedback branch with a time-delay element feeds back the output signal to the inputs with a delay, in such a way that these inputs are prepared for the next change of input signal. The delay time of the time-delay element is greater than the maximum chronological deviation between the two input signals.

Circuit configuration for compensating runtime and pulse-duty-factor differences between two input signals

Ground and power-supply bounce are reduced for a CMOS output buffer. An n-channel driver transistor and a p-channel driver transistor are attached to the output pad. The gate of the n-channel driver transistor is driven by a pre-driver inverter. The pre-driver is a CMOS inverter except that the p-channel source is connected to power through a p-channel and an n-channel source-control transistor in parallel. The n-channel source-control transistor has its gate connected to power so that it remains on. The p-channel source-control transistor has its gate driven by feedback. The feedback is buffered from the output pad, or inverted from the gate of the driver transistor. When the output buffer switches, only the n-channel source-control transistor is initially on, so the current charging the driver gate is limited. The driver turns on slowly at first. Later, the feedback turns on the p-channel source-control transistor, increasing (doubling) the current to charge the driver gate. Thus the driver turns on more rapidly than at first, reducing di/dt and noise. Split driver transistors, and source control on the n-channel transistor are alternatives.

Baohua Chen

Papers

CMOS output buffer with feedback control on sources of pre-driver stage