Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.

Adaptive bias current generation for switched-capacitor circuits

The invention discloses an equalization circuit. The equalization circuit comprises: a high-pass amplifier, which has two differential inputs and two differential outputs, and introduces one zero point; and a transconductance amplifier with feedback, which has two differential inputs and two differential outputs, wherein the inputs of the transconductance amplifier are connected to the outputs of the high-pass amplifier, the outputs of the transconductance amplifier are fed back to the outputs of the high-pass amplifier through two NMOS transistors, another zero point is introduced in a feedback loop of the transconductance amplifier, and the bandwidth is increased by adjusting positions of the two zero points. According to the equalization circuit, the gain of a high frequency part of the equalization circuit can reach 20 dB, so that a larger bandwidth can be achieved, and it is avoided that significant attenuation of the high frequency part occurs in transmission at a high rate; moreover, the circuit is small in occupied area and low in power consumption, relatively.

An equalization circuit

Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal

Active-time dependent bias current generation for switched-capacitor circuits

A high temperature coefficient includes a temperature dependent bias generation circuit serially coupled with a variable resistance. The resistance of the variable resistance device increases with increasing temperature such that the output current of the high temperature coefficient circuit is proportional to the resistance of the variable resistance device.

High temperature coefficient MOS bias generation circuit

Amplifier systems are provided with bias generators that substantially stabilize operating points of system parameters (e.g., drain current and transconductance) over PVT variations, substantially reduce body effects and Early effects, and substantially reduce system output noise. These advantages are realized without significantly increasing system size and/or power consumption.

Amplifier systems with low-noise, constant-transconductance bias generators

A bias circuit (126) is described for use in biasing an operational amplifier (110) to maintain a constant transconductance divided by load capacitance (i.e. a constant gm/CL) despite temperature and process variations and despite body effects. The bias circuit (126) includes a pair of current source devices and a switched capacitor (SC) equivalent resistor circuit (136) for developing an equivalent resistance between the current source devices. By providing an SC equivalent resistor circuit clocked by non-overlapping fixed clock signals, the gm/CL of the bias circuit is maintained substantially constant. Hence, a fixed bandwidth is maintained within the operation amplifier being biased. When employed in connection with operational amplifiers of an SC circuit, the constant bandwidth enables the SC circuit to operate at a constant switching speed despite temp and process variation. Furthermore, by positioning the resistance equivalent circuit (136) between the current source devices of the bias circuit, voltage differentials between the sources are eliminated thereby removing any threshold voltage mismatch and thus compensating for body effect variations.

Bazarjani Seyfollah

Papers

Bias circuit for maintaining a constant value of transconductance divided by load capacitance