This paper reviews architectures and topologies for column-parallel analog-to-digital converters (ADCs) used for CMOS image sensors (CISs) and discusses the performance of CISs using columnparallel ADCs based on figures-of-merit (FoM) with considering noise models which behave differently at low/middle and high pixel-rate regions. Various FoM considering different performance factors are defined. The defined FoM are applied to surveyed data on reported CISs using columnparallel ADCs which are categorized into 4 types; single slope, SAR, cyclic and delta-sigma ADCs. The FoM defined by (noise)2(power)/(pixel-rate) separately for low/middle and high pixel-rate regions well explains the frontline of the CIS’ performance in all the pixel rates. Using the FoM defined by (noise)2(power)/(intrascene dynamic range)(pixel-rate), the effectiveness of recently-reported techniques for extended-dynamic-range CISs is clarified. key words: CMOS image sensor, column-parallel ADC, cyclic ADC, deltasigma modulation, single-slope ADC, SAR ADC, figure of merit

Column-Parallel ADCs for CMOS Image Sensors and Their FoM-Based Evaluations

Dans les reseaux de capteurs urbains, les nœuds emettent des signaux en utilisant plusieurs protocoles de communication qui coexistent. Ces protocoles etant en evolution permanente, une approche orientee radio logicielle semble etre la meilleure maniere d’integrer tous les protocoles sur la passerelle collectant les donnees. Tous les signaux sont donc numerises en une fois. La grande plage dynamique des signaux recus est alors le principal probleme : ceux-ci peuvent etre recus avec une puissance tres variable selon les conditions de propagation. Dans le cas d’une reception simultanee, le Convertisseur Analogique-Numerique (CAN) doit etre capable d’absorber une telle dynamique. Une premiere etude est menee afin d’etablir les caracteristiques requises du CAN sur une passerelle d’un tel reseau de capteurs. La resolution minimale de 21 bits obtenue s’averant trop importante pour etre atteinte au vu de l’etat de l’art actuel, deux approches differentes sont explorees pour reduire la plage dynamique des signaux avant la numerisation. La premiere approche s’appuie sur la technique du companding. Des lois de compression connues sont explorees afin d’etudier leur viabilite dans le cas de la numerisation de signaux multiples, et deux nouvelles implementations sont proposees pour la plus performante d’entre elles. La deuxieme technique proposee consiste en une nouvelle architecture de reception utilisant deux voies de reception. La premiere d’entre elles est dediee au signal le plus fort sur la bande : celui-ci est demodule et sa frequence d’emission est mesuree. A partir de cette mesure, la seconde branche est reconfiguree de maniere a attenuer ce signal fort, en reduisant ainsi la plage dynamique. Les autres signaux sont ensuite numerises sur cette branche avec une resolution du CAN reduite. Cette deuxieme approche semblant plus prometteuse, elle est testee en experimentation. Sa viabilite est demontree avec des scenarios de reception de signaux predefinis representant les pires cas possibles.

https://tel.archives-ouvertes.fr/tel-02402926/document

Une infrastructure flexible de collecte et de traitement de données d’un réseau de capteurs urbain mutualisé

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 M...

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

Analogue Front-End Design for Neural Recording

..........................................................................................................................................i Acknowledgements....................................................................................................................iii List of Tables.........................................................................................................................................................viii List of Figures................................................................................................................................ix Chapter

/pdf/design-fabrication-and-testing-of-monolithic-low-power-aaulsitnev.pdf

Design, Fabrication and Testing of Monolithic Low-Power Passive Sigma-Delta Analog-to-Digital Converters

Abs tra c t—This work surveys various figures-of-merit (FOM) that have been used to evaluate and compare measured ADC performance, and takes a first step towards a systematic classification and analysis. Strengths and weaknesses associated with selected figures-of-merit are discussed, and their potential sweet spots or parametric bias is examined using a combination of theoretical analysis and a near-exhaustive set of scientifically reported experimental data. A commonly used FOM is shown to have a distinct, and highly predictable sweet spot with respect to ENOB, and a strong bias towards scaled manufacturing technologies. It is therefore concluded that a continued discussion and treatment of the topic is motivated.

Bengt E. Jonsson

Papers

Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance