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Bingjun Xiao
Researcher at University of California, Los Angeles
Publications - 23
Citations - 3295
Bingjun Xiao is an academic researcher from University of California, Los Angeles. The author has contributed to research in topics: Programmable logic array & Memory bandwidth. The author has an hindex of 14, co-authored 22 publications receiving 2779 citations. Previous affiliations of Bingjun Xiao include Peking University & University of California.
Papers
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Proceedings ArticleDOI
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
TL;DR: This work implements a CNN accelerator on a VC707 FPGA board and compares it to previous approaches, achieving a peak performance of 61.62 GFLOPS under 100MHz working frequency, which outperform previous approaches significantly.
Patent
Smart electric vehicle (ev) charging and grid integration apparatus and methods
Rajit Gadh,Siddhartha Mal,Shivanand Prabhu,Chi-Cheng Chu,Jay Panchal,Omar Sheikh,Ching-Yen Chung,Lei He,Bingjun Xiao,Yiyu Shi +9 more
TL;DR: In this paper, an expert system manages a power grid wherein charging stations are connected to the power grid, with electric vehicles connected to charging stations, whereby the expert system selectively backfills power from connected electric vehicles to the grid through a grid tie inverter (if present) within the charging stations.
Book ChapterDOI
Minimizing Computation in Convolutional Neural Networks
Jason Cong,Bingjun Xiao +1 more
TL;DR: This work analyzes the linear algebraic properties of CNNs and proposes an algorithmic modification to reduce their computational workload, achieving up to a 47% reduction.
Proceedings ArticleDOI
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration
Jason Cong,Bingjun Xiao +1 more
TL;DR: This paper introduces a novel FPGA architecture with memristor-based reconfiguration (mrFPGA), based on the existing CMOS-compatible Memristor fabrication process, and proposes an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup.
Journal ArticleDOI
FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects
Jason Cong,Bingjun Xiao +1 more
TL;DR: A novel field programmable gate array architecture with resistive random access memory (RRAM)-based programmable interconnects (FPGA-RPI) is introduced which has a 96% smaller footprint, 55% higher performance, and 79% lower power consumptions compared to other FPGA counterparts.