In this work, we introduce a comprehensive methodology for the power integrity/signal integrity analysis of SoC and silicon-based interposers in a HPC platform. By conducting a comprehensive investigation of the global chip-level PDN impact by electrical interactions between the chip, package, and board in the system, an efficient power delivery network was designed to meet HPC specifications. This was achieved by extracting long-term test scenarios (microsecond-order duration) to estimate voltage drop at the bumps and deployment of decoupling capacitors considering the optimal placement and numbers within an allowable cost budget. This analysis also yielded the benefit of reduction in power domains/ball count/package layers which further reduced costs. In addition to the Power Integrity, signal properties were analyzed under the allowed channel conditions (channel width and spacing, shielding lane placement). As a result, the channel design parameters are found to meet the criteria of eye opening including power noise and crosstalk effects. It was demonstrated that the electrical properties of the HBM2e IP are successfully operational up to 3.2Gbps.

PI/SI Analysis and Design Approach for HPC Platform Applications

This work demonstrates an efficient signal integrity (SI) aware routing design method considering system-level SI characteristics floor-planning for 2.5D interposer for the AI/HPC/Network solutions in early stage. The proposed method, system-level SI aware interposer design methodology (SSIDM) can accurately estimate the SI characteristics based on limited design information in early stage and even derive a design guideline for efficient SI aware post-layout design process. Using the novel design guidelines provided in this work can help the designer to smoothly transition designs from HBM2e to HBM3 with sufficient SI margins.

Signal Integrity(SI) aware HBM2e/3 interposer design approach considering y-axis offset between logic and HBM die for HPC/AI/Network applications

The novel design methodology is proposed to find optimal design scheme (routing structure) of die to die interface which ensures the signal quality up to 32Gbps. It explores the design solution space quickly and accurately to find optimal design parameters under PSI constraints such as channel loss and crosstalk limit. Using this design methodology, the optimized die-to-die interconnect design structure is found and implemented on silicon interposer using the obtained parameter values. The proposed approach method is proven to be effective and useful to mitigate the severe channel loss and crosstalk risk in the silicon interposer while meeting the required bandwidth of die-to-die IP implemented in chiplet application.

PSI Design Solutions for High Speed Die-to-Die Interface in Chiplet Applications

In this article, a novel training set optimization method in an artificial neural network (ANN) constructed for high bandwidth interconnects design is proposed based on rigorous probability analysis. In general, the accuracy of an ANN is enhanced by increasing training set size. However, generating large training sets is inevitably time-consuming and resource-demanding, and sometimes even impossible due to limited prototypes or measurement scenarios. Especially, when the number of channels in required design are huge such as graphics double data rate (GDDR) memory and high bandwidth memory (HBM). Therefore, optimizing the training set selection process is crucial to minimizing the training datasets for developing an efficient ANN. According to rigorous mathematical analysis of the uniformity of the training data by probability distribution function, optimization flow of the range selection is proposed to improve accuracy and efficiency. The optimal number of training data samples is further determined by studying the prediction error rates. The performance of the proposed method in terms of accuracy is validated by comparing the scattering parameters of arbitrarily chosen strip and microstrip type GDDR interconnects obtained from EM simulations with those predicted by ANNs using default and the proposed training-set selection methods.

Training Set Optimization in an Artificial Neural Network Constructed for High Bandwidth Interconnects Design

The 2.5D interposer becomes a crucial solution to realize
grand bandwidth of HBM for the increasing data requirement of high
performance computing (HPC) and Artificial Intelligence (AI)
applications. To overcome high speed switching bottleneck caused by the large
resistive and capacitive characteristics of interposer, design methods to
achieve an optimized performance in a limited routing area are proposed. Unlike
the conventional single through silicon via (TSV), considering the reliability,
multiple TSV are used as the robust 3D interconnects for each signal path. An
equivalent model to accurately describe the electrical characteristics of the
multiple TSVs, and a configuration pattern strategy of TSV to mitigate
crosstalk are also proposed.

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Bo Pu

Papers

Design of 2.5D Interposer in High Bandwidth Memory and Through Silicon Via for High Speed Signal