Most memristor-based Pavlov associative memory neural networks strictly require that only simultaneous food and ring appear to generate associative memory. In this article, the time delay is considered, in order to form associative memory when the food stimulus lags behind the ring stimulus for a certain period of time. In addition, the rate of learning can be changed with the length of time between the ring stimulus and food stimulus. A memristive neural network circuit that can realize Pavlov associative memory with time delay is designed and verified by the simulation results. The designed circuit consists of a synapse module, a voltage control module, and a time-delay module. The functions, such as learning, forgetting, fast learning, slow forgetting, and time-delay learning, are implemented by the circuit. The Pavlov associative memory neural network with time-delay learning provides a reference for further development of the brain-like systems.

Memristor-Based Neural Network Circuit of Full-Function Pavlov Associative Memory With Time Delay and Variable Learning Rate

Back propagation (BP) based on stochastic gradient descent is the prevailing method to train multilayer neural networks (MNNs) with hidden layers. However, the existence of the physical separation between memory arrays and arithmetic module makes it inefficient and ineffective to implement BP in conventional digital hardware. Although CMOS may alleviate some problems of the hardware implementation of MNNs, synapses based on CMOS cost too much power and areas in very large scale integrated circuits. As a novel device, memristor shows promises to overcome this shortcoming due to its ability to closely integrate processing and memory. This paper proposes a novel circuit for implementing a synapse based on a memristor and two MOSFET tansistors (p-type and n-type). Compared with a CMOS-only circuit, the proposed one reduced the area consumption by 92%–98%. In addition, we develop a fuzzy method for the adjustment of the learning rates of MNNs, which increases the learning accuracy by 2%–3% compared with a constant learning rate. Meanwhile, the fuzzy adjustment method is robust and insensitive to parameter changes due to the approximate reasoning. Furthermore, the proposed methods can be extended to memristor-based multilayer convolutional neural network for complex tasks. The novel architecture behaves in a human-liking thinking process.

Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks via Fuzzy Method

In this paper, we present a memristor emulator based on voltage difference transconductance amplifier (VDTA). The proposed memristor emulator circuit contains only one VDTA as an active element and single grounded capacitor which benefits from the integrated circuit. Furthermore, it can be utilized MOS-capacitance instead of the external capacitor in the circuit. The complete memristor emulator is laid by using Cadence Environment using TSMC $0.18\ {\boldsymbol \mu }\text{m}$ process parameters. It occupies an area of $35.7\ {\boldsymbol \mu }\text{m}\,\,\times 29\ {\boldsymbol \mu }\text{m}$ . Its simulation results are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner, and radical temperature changes. Moreover, prototype circuit is implemented to confirm the theoretical analysis by employing the single LM13700 commercial device as an active element. Experimental results of the designed memristor emulator are given to investigate its ability for different operating frequencies, the capacitance value and resistor value and DC supply voltage. The experimental results are in accordance with theoretical analyses and simulation results.

Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor

Memristive devices have shown great promise to facilitate the acceleration and improve the power efficiency of Deep Learning (DL) systems. Crossbar architectures constructed using memristive devices can be used to efficiently implement various in-memory computing operations, such as Multiply-Accumulate (MAC) and unrolled-convolutions, which are used extensively in Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs). Currently, there is a lack of a modernized, open source and general high-level simulation platform that can fully integrate any behavioral or experimental memristive device model and its putative non-idealities into crossbar architectures within DL systems. This paper presents such a framework, entitled MemTorch, which adopts a modernized software engineering methodology and integrates directly with the well-known PyTorch Machine Learning (ML) library. We fully detail the public release of MemTorch and its release management, and use it to perform novel simulations of memristive DL systems, which are trained and benchmarked using the CIFAR-10 dataset. Moreover, we present a case study, in which MemTorch is used to simulate a near-sensor in-memory computing system for seizure detection using Pt/Hf/Ti Resistive Random Access Memory (ReRAM) devices. Our open source MemTorch framework can be used and expanded upon by circuit and system designers to conveniently perform customized large-scale memristive DL simulations taking into account various unavoidable device non-idealities, as a preliminary step before circuit-level realization.

MemTorch: An Open-source Simulation Framework for Memristive Deep Learning Systems.

http://iopscience.iop.org/article/10.1088/0256-307X/34/3/038502/pdf

Memristive Behavior Based on Ba-Doped SrTiO 3 Films

In this paper, we propose a novel Verilog-A based memristor model for effective simulation and application. Our proposed model captures desired nonlinear characteristics using voltage-based state control. This model is flexible and accurate, it can exhibit all the behaviors of HP memristive device and a general class memristive device resistive random access memory which is important in logic and memory design. Furthermore, we can antiserially connect two proposed models to capture the ideal ${I}$ – ${V}$ characteristics of complementary resistive switch (CRS). We demonstrate that our proposed CRS model-based crossbar arrays can significantly reduce sneak path currents with high noise margin compared to traditional memristor-based architectures.

Efficient Memristor Model Implementation for Simulation and Application

Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch (CRS)-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.

https://iopscience.iop.org/article/10.1088/1674-1056/25/5/058502/pdf

Bo-Wen Xu

Papers

Efficient Memristor Model Implementation for Simulation and Application

A novel circuit design for complementary resistive switch-based stateful logic operations*