A processor controlled IC component test apparatus adapted to be employed in-line with automatic IC DIP component handling equipment is capable of conducting a preselected verification check of each IC device regardless of the orientation of the DIP in the device contact receptable of the IC handling apparatus. As each device under test (DUT) is inserted into the apparatus test head, a pin-check residual voltage measurement test is conducted to ensure that all the pins of the DUT are in contact with the contact terminals of the test head. If the pin-check test establishes that all the pins of the DUT are in contact with the contact terminals of the test head, a prescribed non-destructive impedance measurement test is carried out in order to determine the orientation of the DIP in the test head. If the device passes the orientation test or is determined by the orientation test to be simply misoriented (inserted upside-down), it is then subjected to a prescribed functionality check (with the direction of orientation taken into account). The processor architecture of the test apparatus is configured to maximize the systems's ability to rapidly sequence through the test vectors for the various DUTs, while also offering the capability to perform traditional CPU functions during the execution of a test. For this purpose, the processor employs a mode-controlled pipelined architecture through which program instructions stored in memory are controllably accessed and processed through either an address-controlled flow path or a data-controlled flow path.

Method and apparatus for testing integrated circuits

A minimal memory in-circuit digital tester with vector memory concentrated in a centralized vector processor circuit, eliminating the need for pin memory. The vector processor circuit memory is partitioned into two blocks, a pointer memory and a change list memory. Every vector clock cycle has one pointer memory entry. The pointer memory entry is an address for the change list memory. The change list memory contains lists of nodes used in the vector test sequence. Each change list entry contains a pin number and several control bits. The control bits define functions such as whether the pin will toggle its data or enable state, whether there are more pins in that particular change list, and whether the list or test has ended. When the end of each change list is reached, all pins that have been primed by that change list will be toggled. The next entry of the pointer memory is then selected which, in turn, selects another, or perhaps the same change list in the change list memory. Each vector within a test vector file corresponds to one entry in the pointer memory, however, several different pointers can address the same change list. As a result, test vector files of great length can be accommodated using minimal memory.

Method and apparatus for a minimal memory in-circuit digital tester

Signature techniques in fault detection and location

The author discusses an implementation of the pin electronics for a distributed architecture (resource-per-pin) printed circuit board test system. Included are descriptions of the custom integrated circuits and hybrids used to accomplish this at a reasonable cost. The pin electronics card which incorporates these custom parts is a relatively sparse looking 16-in by 20.5-in assembly. It is densely routed on six layers using conservative design rules (25-mil line pitch) to achieve the required interconnect. These custom parts allow the automatic compensation for many of the error terms found in a high-performance board test system. The present work demonstrates that it is possible to add significantly to the functionality of printed circuit board test systems through the use of custom integrated circuits. This added functionality can be used to provide new test capabilities and to make existing capabilities easier to use, thereby helping the user meet demanding test requirements. Along with the functionality improvements come equally important accuracy, reliability, and cost benefits. >

Flexible, high-performance pin electronics implementation

A digital in-circuit tester has a test-head controller which controls bursts of test vectors generated by a group of driver-receiver channels, the group of driver-receiver channels responsive to an erase instruction from test-head controller. At least one driver-receiver channel is adapted for nullifying the action of an erase instruction. The driver-receiver channel has a first memory for storing information which determines certain actions of the channel during the next burst of test vectors. The memory is responsive to the erase instruction for being erased. The driver-receiver channel also has an erase inhibitor including: an inhibition-state-retention means responsive to an erase-inhibit instruction from the test-head controller for storing an erase-inhibit logic state; and a combinatorial means communicatively coupled to the inhibition-state-retention means, and responsive to the stored erase-inhibit logic state from the inhibition-state-retention means, and responsive to the test-head controller erase instruction for nullifying the action of the erase instruction.

Bob Illick

Papers

A New Hardware Architecture for Digital In-Circuit Testing.