Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated high-quality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3× faster) and memory footprint (3.3× lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools—showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.

https://dl.acm.org/doi/pdf/10.1145/3388617

VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling

With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of CGRAs. We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.

Trigger circuits and event counters for an IC

A stacked die assembly for an IC includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first integrated circuit die and the second integrated circuit die via the first integrated circuit die avoiding the interconnect restricted area of the first interposer and the second interposer.

Stacked die assembly

In this white paper we provide a vision for 6G Edge Intelligence. Moving towards 5G and beyond the future 6G networks, intelligent solutions utilizing data-driven machine learning and artificial intelligence become crucial for several real-world applications including but not limited to, more efficient manufacturing, novel personal smart device environments and experiences, urban computing and autonomous traffic settings. We present edge computing along with other 6G enablers as a key component to establish the future 2030 intelligent Internet technologies as shown in this series of 6G White Papers. 
In this white paper, we focus in the domains of edge computing infrastructure and platforms, data and edge network management, software development for edge, and real-time and distributed training of ML/AI algorithms, along with security, privacy, pricing, and end-user aspects. We discuss the key enablers and challenges and identify the key research questions for the development of the Intelligent Edge services. As a main outcome of this white paper, we envision a transition from Internet of Things to Intelligent Internet of Intelligent Things and provide a roadmap for development of 6G Intelligent Edge.

6G White Paper on Edge Intelligence

In this paper we describe Xilinx's Versal-Adaptive Compute Acceleration Platform (ACAP). ACAP is a hybrid compute platform that tightly integrates traditional FPGA programmable fabric, software programmable processors and software programmable accelerator engines. ACAP improves over the programmability of traditional reconfigurable platforms by introducing newer compute models in the form of software programmable accelerators and by separating out the data movement architecture from the compute architecture. The Versal architecture includes a host of new capabilities, including a chip-pervasive programmable Network-on-Chip (NoC), Imux Registers, compute shell, more advanced SSIT, adaptive deskew of global clocks, faster configuration, and other new programmable elements as well as enhancements to the CLB and interconnect. We discuss these architectural developments and highlight their key motivations and differences in relation to traditional FPGA architectures.

Xilinx Adaptive Compute Acceleration Platform: Versal TM Architecture

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal-architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in FPGA devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

Network-on-Chip Programmable Platform in VersalTM ACAP Architecture

An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Configuration of a multi-die integrated circuit

Circuits for implementing gating logic in a self-timed integrated circuit. An integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. Each output circuit has a data input coupled to an output of the logic circuit, a gating input, and a data output coupled to an output of the logic block. The output circuit is coupled to place a value on the data input onto the data output when the gating input has a first value and the output circuit receives tokens indicating valid new data on both the data input and the gating input of the output circuit. The output circuit is coupled to leave the data output unchanged when the gating input has a second value and the output circuit receives a token indicating valid new data on both the data and gating inputs of the output circuit.

Gating logic circuits in a self-timed integrated circuit

A cascading output structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes an array of interconnected logic blocks, each including a logic circuit, an output multiplexer, and a select multiplexer. The logic circuit has an input coupled to a logic block input. The output multiplexer has first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input, and an output coupled to a logic block output. The select multiplexer has a first data input coupled to a cascade select input of the logic block, a second data input, and an output coupled to the select input of the output multiplexer. The output of the select multiplexer is also coupled to a cascade select output of the logic block. The cascade select input of the logic block is coupled to the cascade select output of an adjacent logic block.

Brian C. Gaide

Papers

Xilinx Adaptive Compute Acceleration Platform: Versal TM Architecture

Network-on-Chip Programmable Platform in VersalTM ACAP Architecture

Configuration of a multi-die integrated circuit

Gating logic circuits in a self-timed integrated circuit

Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same