N (M+1) combining circuits mathematically arranged into M addition rows and a final carry resolution row so as to form N+M-1 columns, each column having an output, an N-bit multiplicand and an M-bit multiplier being connected to the combining circuits to provide digital, repeated addition type multiplication of the numbers represented by the N and M bits. The combining circuits in the final carry resolution row each have a carry bit input connected to the carry bit output of the previous combining circuit and an inverting amplifier is included in the carry propagation line every three or four combining circuits, to regenerate the carry bit. Further the entire multiplying circuit is formed on a single semiconductor chip and includes N inputs pads and N output pads with input latches and output latches for operating on both the N input bits and the M input bits with very little loss in time.

High speed NXM bit digital, repeated addition type multiplying circuit

A chain-type ripple-carry generating circuit having a plurality of cascaded stages is provided with a regeneration network in each stage for restoring the logic level of a carry signal propagating through the stage. In one embodiment of the invention the regeneration network is designed to restore a carry-not bit and comprises an MOS transistor having its conduction channel coupled between the input of the stage and a ground terminal, the gate of the transistor being driven by a two-input NOR gate, one input of the NOR gate being connected to receive a precharge clock signal and the other input being connected to the input of the stage. When the precharge clock signal is at a logic "0" level and the input of the stage receives a carry-not bit at a logic "0" level, the NOR gate drives the MOS transistor into conduction causing the input of the stage to be pulled to substantially ground potential.

Ripple-carry generating circuit with carry regeneration

Complex logical mechanism, for simultaneously producing output signals related logically to a set of input signals, implemented in transfer gate pairs. The first transfer gate of each pair is connected generally in series and is controlled by conduction according to the signals applied. The second transfer gate of each pair shunts the output node of its related first transfer gate to ground, when enabled by a control signal complementary to the data pattern applied to the first transfer gate of the pair. This direct control of line voltages affirmatively drives the lines or affirmatively grounds the lines to eliminate back circuits. Carry propagation to higher order bit positions is along carry propagate lines, with series connected carry propagate first transfer gates. Order positions not having data values appropriate for carry propagation do not transmit carry values--these transfer gates are not controlled for conduction, but are nonetheless subject to possible back circuits. Carry propagate negation second transfer gates, connected in respective pairs with the carry propagate first transfer gates, are controlled by signals complementary to the control signals for the respectively carry propagate transfer gates, and, when enabled, connect the output nodes of the respective carry propagate first transfer gates directly to ground reference potential.

Carry lookahead logical mechanism using affirmatively referenced transfer gates

A digital adder circuit is disclosed which employs non-DC current configurations to significantly reduce power, device count, and delay in performing binary addition. The circuit features a carry propagate transfer FET device whose gate is controlled by a carry propagate control circuit which selectively gates on the transfer FET device at a particular adder bit stage when the carry-in binary bit is to be transferred as the carry-out binary bit, which takes place when the augend input bit and addend input bit at that stage are not equal. The circuit additionally features a carry generate control circuit which is connected to the carry-out node of the FET transfer device, which selectively connects that node to either a drain potential when both inputs are unity or to ground potential when both inputs are zero, thereby efficiently generating the carry-out bit without regard for the state of the carry-in bit. When the input bits are not equal, the carry generate control circuit has a high impedance state so that it will not affect the propagation of the carry-in bit through the FET transfer device. The resultant adder circuit has a reduced power dissipation, a reduced signal delay, and a reduced device count when compared with prior art FET adder circuits.

Fast, efficient, small adder

Half-adder logic modules employing separate summing and carry circuitry are used in the construction of a modular binary half-adder. Carry bits of less significant digits are calculated independent of and prior to the calculation of corresponding sum bits, thus allowing rapid propagation of such carry bits to more significant digits and subsequent parallel summation of the sum bits using the carry bits previously calculated.

Modular binary half-adder

In a binary parallel complementing L.S.I. adder, a C-MOS transmission gate is provided in each stage with its input and output directly connected to the carry in and carry out leads of the stage. The gate is switched by complementary control bits derived by stage input logic operating on the bits to be summed, whereby very fast passage of a carry through the stages is achieved. The transmission gate consists of p- and n- channel MOS transistors with their sources connected in common to the input and their drain electrodes likewise connected in common to the output.

Brian Jeremy Parsons

Papers

Binary parallel adder employing high speed gating circuitry