The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Apparatuses and methods for performing logical operations using sensing circuitry

A system may perform interconnect BIST (IBIST) testing on source synchronous links. More particularly, the system may perform, at normal operating frequency for the source synchronous link, a source synchronous link test that tests a victim line on the source synchronous link using a transition weave pattern. The transition weave pattern causes interaction between a data transition on the victim line, previous transitions on the victim line, and transitions on the other lines of the link (the 'aggressor' lines). The interaction caused may be: (i) a first crossing pulse on the victim line; (ii) a second crossing pulse of the opposite polarity on each aggressor line concurrent with the first crossing pulse on the victim line; and (iii) a reflection in the opposite direction of the first transition of the first crossing pulse, wherein the reflection results from a previous transition on the victim line. Additionally, in one embodiment, the system may perform repeated iterations of the transition weave pattern while varying the timing of the previous transition on the victim line (to create the reflection) with respect to the first crossing pulse on the victim line.

Source synchronous link integrity validation

An integrated circuit having a receiver that selectively inhibits incoming data from being used to update adaptively generated controls. Sampling circuitry generates a plurality of samples of an incoming signal. Control circuitry generates an inhibit signal in either a first state or a second state according to whether the plurality of samples meets a randomness criterion. Tap weight update circuitry receives the inhibit signal from the control circuitry and updates a plurality of equalizer tap weights based on the plurality of samples if the inhibit signal is in the first state. The tap weight update circuitry refrains from updating the plurality of equalizer tap weights based on the plurality of samples if the inhibit signal is in the second state.

Signaling system with selectively-inhibited adaptive equalization

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

Partial response receiver

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Apparatuses and methods for performing compare operations using sensing circuitry

A system and method for testing signal interconnections using built-in self test (BIST). BIST functionality is designed into the various chips of a computer system. These chips include a transmit unit, a receive unit, a control logic unit, and a central logic unit. A control logic unit associated with a signal block (i.e. a group of signals) configures the signal block for either testing or normal operation. The central logic unit performs test pattern generation for all signal blocks on a given chip. Chips may act as either a master or slave chip during testing. When acting as a master chip, the transmit unit of the chip drives test patterns onto one or more signal lines. The receive unit of the slave chip returns a corresponding test pattern to the master chip after receiving the transmitted test pattern. A receive unit on the master chip receives the corresponding test patterns and performs verification. All tests occur at the operational clock speed of the computer system. A master and a slave chip need not be mounted upon the same circuit board, allowing for tests through connectors within a computer system.

System and method for testing signal interconnections using built-in self test

A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Automated calibration of I/O over a multi-variable eye window

A method and apparatus for operating a source synchronous receiver In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver The clock detect signal may be received by a clock verification circuit The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal The resetting of the source synchronous receiver may be performed locally, and does not reset the core logic of the device in which it is implemented, nor any other source synchronous port on the device Thus, other source synchronous ports on the device, as well as the core logic, may be able to continue operations as normal The method and apparatus may include a source synchronous receiver that is hot-swappable

Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection

A digital process monitor for measuring the performance of an integrated circuit has been developed. The digital process monitor includes: a ring oscillator that generates a series of clocked pulses, and a ripple counter that counts the clocked pulses. The count is measured for a prescribed period of time and the count corresponds to the performance of the integrated circuit.

Brian L. Smith

Papers

Source synchronous link integrity validation

System and method for testing signal interconnections using built-in self test

Automated calibration of I/O over a multi-variable eye window

Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection

Digital process monitor